Cycle by Cycle Problem?

["Bryan Parkoff" <none@nospam.net>]

    Real Apple II machine always run 6502 CPU at 1MHz and NTSC at 14MHz at
the same time.  6502 CPU depends on clock system in its own.  Also NTSC
depends on clock system alone.  It means that both 6502 CPU and NTSC can't
share the clock system at the same time.  It looks like that there is more
than two clock system which they can operate independently at the same time.
    The fact is that 6502 CPU runs at exact 1,020,484 Hz per second and NTSC
runs 17030 cycles * 60 frames = 1,021,800 video Hz per second.  It does not
look to be exact 60 vertical Hz, but it is supposed to be 59.92 vertical Hz.
Then it should be (17030 cycles * 59 frames) + 15714 cycles = 1,020,484 Hz
(6502 CPU) per second.
    Why do you expect to be perfect NTSC's vertical 60Hz to match 6502 CPU?
What if you run 6502 CPU at 2,040,968 Hz (2 MHz) using Transwarp card or Zip
card while NTSC runs at 14MHz at the same time?  It is impossible to capture
one 6502 CPU cycle as video cycle before it is converted to 14 pixels as 14
cycles for 14MHz.  It may read first video cycle and ignore second video
cycle at 2MHz.  If it is 6502 CPU at 4MHz, it will read first video cycle,
but it ignores second, third, and fourth video cycle.  It is same example
that NTSC can't reduce from 60 frames to 30 frames at 6502 CPU 2 MHz or from
60 frames to 15 frames at 6502 CPU 4 MHz.  Is it the way how clock system
can take care of 6502 CPU and NTSC independently?
    The reason is that I am asking because Apple II Emulator can't be done
independently.  Real Apple II machine can do to use parallel time as
independent clock system, but Apple II Emulator has to use serial time as
dependent clock system.  It is because x86 machine or other machine has to
execute one instruction at this time.  It is impossible to execute two
instructions at the same time (It is not about x86's optimization solution.)
It has to execute x86 instructions to emulate 6502 CPU first before it
begins to execute other x86 instructions to emulate NTSC second at step by
step time.
    The only best solution is what emulation documentation states to count
emulated CPU's cycles before emulated CPU's cycles reach the maximum number
of cycles to respond the video update.  It would be big pain to manipulate
the number of cycles with one dependent clock system.
    I would try to capture PC's clock system rather than cycle counter.  It
can count msec or nsec to respond 6502 CPU or NTSC.  Have you tried your
experiment in your own project before?  I try to make emulation act like
real machine which it will respond to sound, Disk II's spinning mechanism,
memory refresh timing, and general timing from crystal osc chip.
    It is like two applications running at the same time.  It would be first
application as 6502 CPU and second application as NTSC at the same time, but
first application must be performed first before second application like I
stated step by step x86 instructions.  It can't be true multi-tasking at the
same time as 1000 msec, but it can do at the same time at 1 sec.  Is it
possible that I can implement multi-tasking to sustain 6502 CPU and NTSC,
and more like sound and Disk II's spinning mechanism?
    Please advise how to overcome the emulation's limitation into acting
like real machine?

Bryan Parkoff