Michael J. Mahon wrote:
Bill Garber wrote:Sorry Mike, but only 4 MB is directly accessible. To get to 8MB or more, that 4MB is banked and switched by accessing the ROM memory manager.I was under the impression that 8MB of the address space was devoted to RAM and 8MB to ROM.
Um, the IIgs memory manager uses 64k 'Banks' to divide the ram, but it is not bank switched. When going through the memory manager, the upper address lines are latched into a 'bank select' because the CPU does not have enough legs for the address and data lines. The upper memory address uses the data lines and get latched off via the memory manager. Only 4 megs of RAM are supported through the banks in this way. The Ram slot also only provides enough refresh select lines to deal with 4 megabytes of ram.
The extra circuitry on the larger cards divides the RAM into a couple of banks of 4M or less to allow the refresh to be done on all RAM. It also acts as a memory manager to supply the proper upper memory 'bank' decoding. Quite a timing trick to capture the upper address line off the data lines, ask DMA! Then consider the Rom1 has 4 banks on the main board and the Rom3 has 16 banks. Nothing but FUN in that design!
I still say build an accelerator consisting of a CPU and linear 16M RAM and Load the ROMS into RAM, mirror Banks 0 and 1 to the main board only during Video RAM access.
Thankx, Ed