[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: How many times must Apple make such DRASTIC architecture changes?

Paul Schlyter wrote:
In article <lQw*bgOQq@news.chiark.greenend.org.uk>, timc@chiark.greenend.org.uk says... 



Clock speed isn't rising very fast now, but performance and clockspeed
are only loosely related anyway.  At the bioinformatics applications I
deal with in my day job, a 1.6 GHz Intel Itanium2 is roughly 50% faster
than a 2.8 GHz Xeon, running the same suite of programs, and in both cases
compiled with Intel's compiler.



....and if the run time had been exactly proportional to clock speed, it
ought to have run 75% faster.  And 50% faster isn't that far off....


I think you missed the sense of the difference.

The 1.6MHz Itanium2 is 50% _faster_ than the 2.8Mhz Xeon.

The difference reflects the higher level of realized parallelism
in the Itanium2 relative to the Xeon.

In the larger context...

"Moore's Law" relates to the scaling of silicon feature size and
the maximum usable die size, and is actually an economic prediction
that the value delivered by rapidly increasing capabilities will
finance the effort required to develop those capabilities.

That this is possible with silicon chips is a consequence of the
extreme crystalline "smoothness" of hyper-pure silicon across
several orders of magnitude of physical scale.

As the number of transistors on a chip rises exponentially, the
degree of computational parallelism that can be supported (by
pipelining, wider data paths, superscalar implementation,
multi-threading, VLIW, etc.) increases, increasing the
"work done per cycle".

As silicon feature size decreases, the realizable clock speed
increases, increasing the "cycles per unit of time".

Processor performance, or "work done per unit of time" is the product
of these two factors.  Historically, the advances in silicon technology
delivered about a factor of two in perfomance every 18 months, but
as physical/process limits are being approached, and as the cost of
a new process fab continues to grow (also exponentially), the rate
of increase of uniprocessor performance has slowed.

This is not an unexpected result, since there is not an unlimited
amount of parallelism to be discovered in traditional single-thread
computer algorithms, and power dissipation limits clock speed on
large chips.

The expected (hoped for) solution to this problem is the growth of
highly parallel, multi-computer algorithms, which would rely less
on shared memory and more on fast message passing.

Multiple-core processing chips are the natural economic adaptation
to this hope (which remains largely unrealized in desktop applications).

-michael

8-voice music synthesizer using NadaNet networking!
Home page:  http://members.aol.com/MJMahon/