Re: about accelerator chips/cards

[mjmahon@aol.com (Michael J. Mahon)]

damage_x@hotmail.com replied:

>Michael J. Mahon wrote:
>>
>> An accelerator using the same principles could be used for almost
>> any machine, but the ones designed for Apple II's are specialized
>> in the way that they are controlled.
>
>I thought it was interesting that they actually had cache RAM attached
>to a 65xx. The 65816 upgrades for the C=64 simply run at 1MHz in the
>old 64K address space and run at 20MHz when working above 64K. Alas the
>Atari 8-bit world doesn't seem to have any sort of standard CPU
>upgrade.

Caching the low-64K wold allow faster operation, but there may also
be timing constraints that must be maintained.  Of course, any bus
interactions with the rest of the system must run at standard speed.

>> The modes and registers in the Rocket Chip (and the Zip Chip, of
>> which it is a clone) are accessed by multiple references to certain
>> addresses which are mapped to I/O space in the Apple II.  And the
>> chip monitors certain I/O addresses to slow down for sequences of
>> instructions which are timing-critical (such as 5.25" disk access in
>> the Apple II).  These features are specialized to the Apple II architecture.
>
>So software on another system with a different memory map could
>accidentally mess with the chip config...

Exactly--though the reference sequences required to "unlock" the
access are very improbable.

>> Under the right conditions, one of these chips might work in another
>> 1MHz 65C02 machine, depending on whether speed-critical routines
>> were involved and how the address space was allocated.
>
>Would it have to be 1MHz or is the accelerated speed derived from the
>1MHz perhaps?

The internal clock is derived from an internal crystal oscillator, but
the timings for bus transactions all assume a 1MHz environment.

>Any differences with the cards vs. the chips?

Cards came in both cached and "full memory" designs. The "full
memory" cards just put 64K or more of fast memory on the card and
treated it as a complete "cache" of system memory.  This simplified
the control somewhat, at the cost of limiting the amount of memory
that could be accelerated (since many cache-based designs had
enough tag width to accelerate more than a megabyte of system
memory).  Of course, any caching scheme for bank-switched memory
must be aware of the bank switching controls and "shadow" them.
The Zip Chip and Rocket Chip do this for the most common Apple II
memory expansion architecture.

-michael

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