Re: Does an enhanced //e _ALWAYS_ have 80 col. support?

[mjmahon@aol.com (Michael J. Mahon)]

Andy McFadden wrote:

>Don Bruder <dakidd@sonic.net> wrote:
>> Right, that's what I was referring to. When in doubt, the "rule" I 
>> always knew was "read unless specifically told otherwise". 
>
>Apple II reference manual (1981 edition), page 20:
>
>  A program can "reference" the address of the special location for the
>  speaker by performing a "read" or "write" operation to that address.
>  The data which are read or written are irrelevant, as it is the
>  _address_ which throws the switch.  Note that a "write" operation on the
>  Apple's 6502 microprocessor actually performs a "read" before the
>  "write", so that if you use a "write" operation to flip any soft
>  switch, you will actually throw that switch _twice_.  For toggle-type
>  soft switches, such as the speaker switch, this means that a "write"
>  operation to the special location controlling the switch will leave
>  the switch in the same state it was in before the operation was
>  performed.
>
>I just now tried a very simple sound loop on a real IIgs.  There was no
>difference for "LDA $C030" vs. "STA $C030".

Right.

And now I know the source of the misconception about _all_ 
stores...  I'd have expected a generalization of this sort in the
Applesoft manual, but I'm surprised that someone didn't catch
the error in the Reference Manual.

Just for the record, consider that a store absolute takes 4 cycles,
three to read the instruction and one to write the target address--so
there's no time for an extra access.

The indexed forms take a cycle to add the index and present
the (non-page crossing) address to the bus, which, since read
data arrives late in the cycle, allows the indexed loads to
complete on the fourth cycle.

But the stores are not able to present the required data at the
beginning of the fourth cycle, since the register read bus is busy
with the index value.  Therefore, they do a "harmless" memory
read cycle, followed by the write with the appropriate data on
the data bus.

If there is a page crossing as a result of indexing, then the first
read access is to the address one page lower than the actual
effective address, since the carry hasn't yet been propagated.

-michael

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