Re: Accelerator / VGA Graphics card

["brad" <mrbrad@ll.net>]

just lurking here... but if the "Woz" is watching..do we have a nice little
hardware project to propose for you!!!!!!!!

i mean everyone else is into retro computing....why not you as well

my 2c worth

back to discussion at hand

brad





"Sheldon Simms" <sheldonsimms@yahoo.com> wrote in message
pan.2003.10.25.18.55.39.204261@yahoo.com">news:pan.2003.10.25.18.55.39.204261@yahoo.com...
> On Sat, 25 Oct 2003 06:51:35 +0000, Michael J. Mahon wrote:
>
> > Sheldon Simms replied:
> >
> >>On Fri, 24 Oct 2003 21:56:34 +0000, Michael J. Mahon wrote:
> >>
> >>> Sheldon Simms wrote:
> >>>
> >>>>On Fri, 24 Oct 2003 14:59:39 -0400, Charlie wrote:
> >>>
> >>> <snip>
> >>>
> >>>>> That makes sense and I like the idea of the 1MHz clock generating an
> >>>>> interrupt on the card.  Wouldn't this free up the emulator to do
other
> >>>>> things (graphics) in between interrupts?
> >>>>
> >>>>Well yes, but it would probably do everything it needs to do and then
> >>>>still be waiting around.
> >>>
> >>> Have you checked out how long the Pentium M requires to take an
> >>> interrupt and restore state and return?  I'll bet that caches are much
> >>> less helpful for this than you imagine, and _lots_ of cycles are
needed.
> >>
> >>After reading this I poked around a bit in Intel documentation but
> >>they are not very forthcoming. However, considering the front side
> >>bus frequency of 400Mhz, and the fact that all code on the Pentium M
> >>would be running in supervisor mode (i.e. - no need to change protection
> >>level), I have a hard time believing that it couldn't handle a 1Mhz
> >>interrupt source. But perhaps I'm wrong. In that case other measures
> >>would be required.
> >
> > Note that FSB speed only applies to burst transfers from RAM to and
> > from cache, and does not include the startup latency, which is probably
> > 50-60ns.
> >
> > I'm not saying that the processor can't handle interrupts at a 1MHz
> > rate, but I am saying that it may use a lot bigger fraction of the
> > processor's time than a first reading of the specs might suggest.
>
> Well another option would be to have a bus-width bank of shift
> registers (a shift-memory, if you will). The emulation code writes
> the entire bus transaction out to this memory which is then clocked
> out onto the bus by the 1Mhz clock.
>
> > If you're into computing for speed, Apple II's are a terribly
> > inefficient way to get there.  ;-)
> >
> > And if you're into computing for fun, Apple II's will get you
> > there at a very enjoyable speed.
>
> Well fun is the point of this card too. I'm not planning on replacing
> my PC with an 80 Mhz IIgs...
>
> -Sheldon
>
>
>