Re: Apple, Jobs, and the irony of it

[mjmahon@aol.com (Michael J. Mahon)]

Eric Smith replied:

>mjmahon@aol.com (Michael J. Mahon) writes:
>> There is a certain irony here, in that both AMD and Intel
>> implementations of the IA-32 architecture, in their current
>> 32-bit chips, do not run the IA-32 instructions "as written".
>
>Huh?  There have been processors for more than forty years that have not
>been hardwired to execute the documented user-level instruction set.
>The microarchitectures have gotten a lot more complex over those forty
>years [*], but I don't think it's fair to claim that a Pentium Pro/2/3/4
>or Athlon doesn't execute IA-32 instructions "as written".  If AMD,
>Intel, Nexgen, and Transmeta hadn't bragged about how clever their
>microarchitectures are, you wouldn't even be thinking about making such
>a statement.
>
>The fact is that these chips DO execute IA-32 instructions "as written".
>The way they execute them just happens to be very complex.

Yes, but the point I was making is that the actual execution
machinery on the chip is _not_ IA-32 machinery--only the fetch/
decode/translate-to-internal-code part even knows about IA-32.
(And yes, I realize that _all_ IA-32 implementations have actually
been microcoded simulations of IA-32 on simpler hardware.)

Further, the IA-32 code analysis/translation parts are needed
only because of IA-32 compatibility, and could be dispensed with
in a more modern design.  These parts of the implementation
1) represent additional complexity not required at execution
time, and 2) are doing a partial parallization job on-the-fly with
very limited knowledge and resources, compared to what a
modern optimizing compiler can bring to bear.

As just one example, the IA-32 architecture has a very small
register set, leading to very frequent false dependencies between
IA-32 instructions.  Modern implementations attempt to remove
many of these dependencies by renaming the IA-32 registers into
a much larger set of general registers actually used by the
execution engine.  This dynamic renaming requires pipeline stage(s)
and silicon which could be better employed if the compiled code
were not restricted to the IA-32 instruction set architecture, so
that renaming was not required.

One of the reasons that Itanium I and II implement IA-32 compatibility
"on the side" is so that the compatibility capability does not distort
the design of the chip excessively from its native VLIW-like intent
(which is capable of much greater performance).

Considering that the "typical" PC in use is a 500MHz Pentium III,
the need for extreme compatibility-mode performance during the
architecture transition is dubious.

-michael

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