Thanks, it should be a nice project if I get it working. I think there
might even be a commercial market for a 20 MHz IIgs accelerator board.
The general plan is to study the approaches used by the Zip GSX and the
TranswarpGS and to simplify the design. Aesthetically, the difference
between the two is amazing. The Transwarp looks like a nightmare to
manufacture, with DIP switches and a daughterboard.
In comparison, the GSX is such a clean card that it is practically a work of
art. The circuit traces are laid out in nice organized patterns, it looks
like they minimized the path length for the circuit routing, and the
on-board memory layout is a model of how to conserve space.
As I understand the two design philosophies, the Zip plan was to recreate
the II on the card, whereas the Transwarp approach was to fetch instructions
and data for the cache, process on the card, and to use a type of glue logic
(implemented in gate arrays) to look for memory accesses or instruction
combinations that require the processor to slow down.
If anybody knows where I can find some of the engineering documents for
either of these cards, I would love to study them.