Re: Low-level vs. High-level programming (was My First Computer)

[mjmahon@aol.com (Michael J. Mahon)]

Paul Schlyter replied:

>In article <20030619155811.09031.00001456@mb-m18.aol.com>,
>Michael J. Mahon <mjmahon@aol.com> wrote:
>> Paul Schlyter wrote:
>> 
>>> In article <Xns939FA7E65252wildstar128hotmailco@216.168.3.44>,
>>> wildstar  <wildstar128@hotmail.com> wrote:
>>> 
>>>> Excuse me, one has to first write/compile a JAVA compiler. It still 
>>>> requires interpretation during execution. Did you forget about the byte-
>>>> code interpretation. That is like converting tokens in token BASIC.
>>> 
>>> Note quite: Java bytecode is much closer to machine language than BASIC
>>> tokens.
>>> 
>>> Actually, even native machine code is interpreted -- by the hardware
>>> CPU.  If you want to look at some REAL machine code, then you'll have
>>> to look at the microcode om ROM's within many CPU's.
>> 
>> Or look at the machine code of a RISC machine, which directly
>> controls the hardware.
> 
>Really?  I knew that each instruction for a given RISC CPU always has
>the same length, but I wasn't aware that these instructions were so
>very long (hundreds of bits, or more).  Yep, that's the kind of
>instruction lengths you need if you want a specific bit in the
>instruction to directly control a specific gate in the hardware --
>that's what microcode does.

I didn't say that each bit of the RISC instruction directly controls a
gate.  But they do control the gates without the intervention of any
intermediate microcode state sequencer or ROM (though modern
decode PLAs are similar to ROMs in many respects).

As with any hardware control where code space is a consideration,
RISC instructions are decoded in multiple parallel layers of hard
logic (including PLAs) to produce the control signals for the datapath.

Microcode architectures come in two main distinctions:  vertical
and horizontal.  Vertical microcode has short instructions and is
executed by a sequential state machine that typically requires
several clocks to process one "machine instruction".  Horizontal
microcode has very long instructions, and often requires just a
few, or only one, cycle to process one "machine instruction"

RISC was primarily a reaction against the continuing use of deep
vertical microprogramming to implement "high level" machine
instructions, like storage-to-storage operations.  Horizontal
microprogramming, when used to implement such CISC
architectures, also must provide for the myriad of possible
exceptions that must be anticipated and handled, such as
multiple TLB/page faults on a single instruction.

Horizontal microcode which runs at one cycle per machine
instruction is really just a decoding convenience, and not a
separate state machine interpreting the machne language.

Vertical microprogramming was a great idea when logic
became solid state and fast while memory remained
magnetic and slow.  With the advent of cache memories
that can deliver data and instructions in single logic cycles,
the vertical microprogram became an unnecessary obstacle
to peak performance.

An irony is that with the relentless density increases
delivered by Moore's "Law", the inefficiencies of CISC
architectures get plastered over by the surfeit of logic,
which can "JIT-compile" CISC instructions to RISC
instructions in an internal I-cache.  ;-)

-michael

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