Re: When to use a 74LS245 to buffer the data bus?

["Peter Ibbotson" <spambox@ibbotson.demon.co.uk>]

"Glenn Jones" <rg.jones@rogers.com> wrote in message
news:v_Eta.112009$kYH.13047@news01.bloor.is.net.cable.rogers.com...
> Yves, I am interfacing an ethernet module to the Apple2 bus. The module
has
> two chips on it...one is a custom chip W3100A and the other is a RTL8201L
> PHYceiver chip. I am not sure how many TTL inputs this would be equivilent
> too.
>
> The concept is the same as the TFE ethernet board that Adam Dunkels
created
> except that the Wiznet chip is amost 1/4 the price and has a TCP/IP stack
> built into the 3100A.
>
> I have a prototype wired up without the 74LS245 but IIgs hardware
reference
> pg 180 talks about loading and driving rules and this has got me thinking
> htat maybe I should be using a 74LS245 for the data bus.
>
> If you are interested, you can find out more information about my project
at
> http://members.rogers.com/rg.jones/AppleII_ethernet%20_project.htm


In practice you shouldn't need it, however it may well help you to work
"correctly" with respect to bus timing issues and overshoot/undershoot on
the bus.
You may well find the hold times on the outputs of your ethernet chip are
too short for the technology used on a GS, sticking a buffer in the way will
extend the hold time.
Personally I'd be tempted if you're doing a PCB to put the 245 on the board
and then put jumpers across the buffers if the chips not present.

--
Work peteri@lakeview.co.uk.plugh.org | remove magic word .org to reply
Home peter@ibbotson.co.uk.plugh.org  | I own the domain but theres no MX