Re: 14MHz Osc Chip Question

["Bryan Parkoff" <BParkoff@satx.rr.com>]

    I seem to understand, but you did not answer my question.  What do clock
pulse and cycle mean?

    I understand that Hertz is the same as Cycle.  Hertz only executes each
one second.  It is what the dictionary said, but it is probably wrong.  If
it is possible, Hertz is truly to be executed each one millisecond.  It
should be .001 cycle each one second.  It would be 1,000,000 cycles per
second or 1MHz.  Minimum 142,857 instructions are executed each one second.
Maximum 500,000 instructions are executed each one second.  Average 222,222
instructions between 142,857 and 500,000 instructions are executed each one
second.  Does it make sense?

--
Yours Truly,

Bryan Parkoff
BParkoff@satx.rr.com
"Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message
qh1xztrnnf.fsf@ruckus.brouhaha.com">news:qh1xztrnnf.fsf@ruckus.brouhaha.com...
> "Bryan Parkoff" <BParkoff@satx.rr.com> writes:
> >     If TransWarp or ZipCard are used, do they disable 14.318 MHz crystal
> > chip while another higher crystal chip is executing for 6502 CPU?
>
> No.  They run a separate CPU at a higher speed on the card.  They don't
> interfere with the timing of the main logic board, as that would break
> the video.
>
> > What is
> > the difference that Apple IIgs operate?
>
> The IIgs has much more complex circuitry (buried in the ASICs) that allow
> the CPU and memory to be run at a higher frequency than the video.  The
> earlier Apple II models do not have this capability.
>
> >     If I understand correctly, only ONE cycle can be executed at once
time
> > each second on 6502 CPU.  Does 65 cycles execute for one minute?  I am
> > confused the words, "CPU Clock and Cycle".
>
> The 6502 can perform one memory access for every clock cycle, so it can
> perform just a bit over one million memory cycles per second in the
> Apple II.  (More on the IIgs due to the fancier circuitry).
>
> That's approximately one CPU cycle per microsecond, not one per second.
>                                        ^^^^^
>
> >     I do understand that 0.5 cycle can be executed for 6502 CPU BEFORE
(NOT
> > WHILE) another 0.5 cycle can be executed for RAM.  Both 0.5 cycles are
equal
> > to one cycle each second.  It is the way that 6502 CPU is enabled to
execute
> > 0.5 cycle before it is disabled.  Then RAM is enabled to execute 0.5
cycle
> > before it is disabled.  It does repeat both 6502 CPU and RAM over and
over
> > that it becomes one cycle per second.  Does it make sense?
>
> I think you've got the right idea, other than it being two RAM cycles per
> microsecond, one for video and one for the CPU.