Re: 14MHz Osc Chip Question

[dempson@actrix.gen.nz (David Empson)]

Bryan Parkoff <BParkoff@satx.rr.com> wrote:

> > What makes you think that?  If you replace the 14.318 MHz crystal in an
> > Apple ][, ][+, //e, or //c with a higher frequency, all the machine
> > timing including video will change, because it's all derived from that
> > 14.318 MHz crystal.  Almost everything in the computer, including some
> > peripherals like the floppy controller, are carefully designed based on
> > the precise timing.  Basically most everything won't work at a different
> > frequency.
>     If TransWarp or ZipCard are used, do they disable 14.318 MHz crystal
> chip while another higher crystal chip is executing for 6502 CPU?

No.  Accelerators have their own on-board (or on-chip) crystal which
controls the maximum speed of the accelerator and hence the 65C02 CPU.
The rest of the motherboard continues to operate from the 14.318 MHz
crystal.

Whenever the CPU on the accelerator needs to access a non-cached memory
location (including any I/O access), the accelerator must synchronize
with the motherboard clock.  For the ZipChip (and ZipGS), this includes
all write cycles, but read cycles for memory locations which have
already been cached do not require synchronization.

The accelerators also have a complex scheme of slowing down to remain in
sync with the motherboard when selected I/O accesses occur, so that
software timing loops (such as disk I/O) will operate correctly.

> What is the difference that Apple IIgs operate?

The IIgs master clock is 28.63636 MHz, which is double the 14.31818 MHz
crystal of the 8-bit machines.  All the standard Apple II clock
frequencies are derived from this.

The IIgs is also able to operate part of its memory and I/O system at
"fast" speed (about 2.8 MHz), namely RAM banks $00 through $7F (8
megabytes), the ROM and a few of the I/O registers in the "fast
processor interface" chip.  The "fast" RAM banks are refreshed by
stealing cycles from the CPU, which reduces the average effective clock
speed to about 2.5 MHz when executing code from RAM. (ROM accesses
aren't interrupted by refresh cycles, so code in ROM can run a little
faster than code in RAM.)  If the IIgs is set to run in "slow" mode then
the entire address space is accessed at 1.023 MHz, and "fast" RAM
refreshing occurs during the unused half of CPU cycles.

The remaining 128KB RAM area (banks $E0 and $E1) and most of the I/O
system always run at "slow" speed (1.023 MHz, the same as an 8-bit Apple
II), and operates exactly like a 128K IIe, including being refreshed as
a side effect of the memory accesses by the video system.

> > The 14.31818 MHz clock is divided by 14 to produce the CPU clock.  (One
> > out of every 65 CPU clocks is stretched a bit, but we can ignore that
> > for now.)  The resulting signal has a period of 978 ns.  It spends about
> > 489 ns high and 489 ns low (actually slightly less since the transistion
> > takes a few ns).  The 6502 only uses the half of the cycle when the clock
> > is high to perform a memory access.  The Apple circuitry uses the other
> half
> > of the cycle, while the clock is low, to perform a memory access for video
> > (and memory refresh).
>     If I understand correctly, only ONE cycle can be executed at once time
> each second on 6502 CPU.  Does 65 cycles execute for one minute?  I am
> confused the words, "CPU Clock and Cycle".

A "CPU cycle" is one period of the clock being fed into the Phi0 and
Phi1 pins on the 6502 or 65C02.

The base CPU clock frequency of the NTSC models of the Apple II is
14.31818 MHz / 14 = 1.0227271429... MHz. (For PAL models, it is 14.25
MHz / 14 = 1.0178571429... MHz.)

Every 65th CPU cycle is stretched by two periods of the 14M master
clock, so the average clock frequency for NTSC is 14.31818*65/(65*14+2)
= 1.02048 MHz (assuming I have the formula right - can't be bothered
checking it right now).

This means that the 6502 or 65C02 will execute about 1.02 million CPU
cycles per second.  Given a minimum instruction time of 2 CPU cycles and
a maximum of 7, the CPU can execute between 145700 and 510000
instructions per second, and will perform a maximum of 1.02 million
memory accesses per second (including instruction fetches, data accesses
and wasted cycles due to internal operations).

At the same time, the video system will be accessing memory in the half
of each CPU cycle during which the CPU is not accessing memory, so the
video system will also be performing 1.02 million memory accesses per
second, for a grand total of 2.04 million memory accesses per second.

>     I do understand that 0.5 cycle can be executed for 6502 CPU BEFORE (NOT
> WHILE) another 0.5 cycle can be executed for RAM.  Both 0.5 cycles are equal
> to one cycle each second.

No, they are equal to one cycle of whatever frequency the clock is
running at (1.02 MHz), so one cycle is about 970 nanoseconds
(0.000000970 seconds), not one second.

The other half of each cycle is used for the video display, which
happens to refresh the RAM, so it would be better to describe it as "0.5
cycle for the CPU and 0.5 cycle for video".

-- 
David Empson
dempson@actrix.gen.nz