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Re: Apple //c+ questions...
- Subject: Re: Apple //c+ questions...
- From: mjmahon@aol.com (Michael J. Mahon)
- Date: 01 Apr 2003 20:34:52 GMT
- Newsgroups: comp.sys.apple2
- Organization: AOL http://www.aol.com
- References: <b6covv$dau$05$1@news.t-online.com>
- Xref: archiver1.google.com comp.sys.apple2:29349
In article <b6covv$dau$05$1@news.t-online.com>, "Marcus" <test@supercarrier.de>
writes:
>found on www.apple-history-com:
>
>---cut---
>The Apple IIc Plus (identified as ROM '5') was the first IIc model to see
>significant changes.
<snip>
>the equivalent of a ZipChip 4 MHz accelerator built-in. Apple licensed the
>add-on technology from Zip Technologies to incorporate the accelerator as
>standard in the IIc+, though in doing so, broke it out into an ASIC, SRAM
>and a faster 65C02 (the ZipChip had all that intergrated into a tall 40-pin
>DIP chip).
Just for the record, the //c+ implementation is logically identical to the
Zip Chip. The Zip Chip just packaged the processor, clock, ASIC, and
SRAM together on a multi-chip module and potted it as a 40-pin DIP.
In other words, the same multi-chip implementation is used, just
packaged differently.
-michael
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