Re: ZipGS question

[Rubywand <rubywand@swbell.net>]

Jeff Blakeney writes ...
> 
> On Mon, 03 Mar 2003 11:50:07 GMT, Rubywand <rubywand@swbell.net>
> wrote:
> 
 ....
> 
> >     The method for addressing memory beyond 4MB on the cards is a
> >kludge; and, users are constantly experimenting to discover whether
> >or not some system problem is related to non-support for the extra
> >RAM.
> 
> I wouldn't say it is a kludge.  If I remember correctly, Apple said
> that the max memory that the IIgs memory expansion slot can handle is
> 4 MB is because they only put address decoding circuitry on the
> motherboard to handle decoding 4 banks of RAM.  This is why, if your
> memory card uses those bank select lines, you are limited to 256 KB,
> 512 KB, 768 KB or 1MB if using 256 Kb memory chips or 1 MB, 2 MB, 3 MB
> or 4 MB if using 1 Mb memory chips.
>
> If the memory card doesn't bother using those bank select lines and
> instead decodes the memory address directly from the address lines
> then there is no reason why the memory expansion connector cannot be
> used to support up to 16 MB of memory.
 ....

     It seems like the problem is that the complete address is only
available on the Address lines for up to 4MB-- you have 20 bits (1MB)
plus two lines to select 1 of 4 banks.

     A workaround is to pick off bank information from the Data lines.
There's a good discussion in IIgs Technote #21 Glenn A. Baxter and
Jim Merritt ...

>>
....
Suppose a card were designed to latch the bank address directly from the data 
bus with the rising edge of the PH2 clock signal.  It could use the bank 
address to derive the proper RAM row address and never bother with CROW0 and 
CROW1 at all.  Directly latching the bank address would permit the card to 
accommodate any desired RAM arrangement in 64K increments, including an odd 
number of rows.  Although the technique is valid during CPU cycles, it does 
not work during DMA cycles since the FPI never emits the DMA bank address onto 
the data bus.  During DMA cycles, any card that tries to latch the bank 
address directly, instead latches the bank address that was put on the data 
bus during the last CPU cycle, which is probably the wrong value.
....
<<

     A possible fix could be some little module tacked onto the motherboard
which supplements the FPI and produces additional bank select lines.



Rubywand