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Re: Opcode Instruction Question
Mike wrote:
>
> Bryan Parkoff wrote:
>
> > 256 Opcodes vs 65536 Opcodes
> >
> > I do not talk about operand that can range from 8 bit through 32 bit
> > and
> > beyond. I only talk about the opcode. Opcode is only 8 bit which 65xxx
> > CPU
> > can hold up to 256 opcodes. My question is--how is it possible that
> > another CPU such as Intel can hold more than 256 opcodes (perhaps 300
> > opcodes).
> >>256 opcodes use 16 bits because >256 opcodes uses two hex codes while <256
> > opcodes use only one hex codes (8 bit). Do you know what I am talking
> > about? Please advise.
> >
>
> The 80x86, for example, (and even the Z80, I believe) can use an "opcode
> prefix" which changes the meaning of the next byte read as an opcode, thus
> giving an effectively larger variable-length instruction set. It is
> important to note that on the Intel x86 (386 and above), the CISC
> instructions are broken down into smaller parts and run by microcode.
> Theoretically, Intel could create rather flexible, complex instructions,
> but in practice is not feasable.
>
> Other processors (the 68000, for example) use a full 16 bits for the
> opcode, and fetch it as one piece. What the person before you was saying
> is that since not all 16-bit combinations are used, some of them can be
> used to store all or part of an operand.
>
> Hope this clears things up a little.
>
> Mike
On the 68K the operand encodes a lot in those 16 bits, but the opcode is
fixed to 16-bits.
For further information:
Subtraction Instruction where each character is a "bit"
Subtract:
SUB 1001 REG D SZ EFFADR
Subtract on Address Reg:
SUBA 1001 REG S 11 EFFADR { S is 1 = long, 0 = word operations }
Subtract Immediate:
SUBI 0000 010 0 SZ EFFADR { byte, word, or long following depending
on sz}
Subtract Quick (0,7) as a value
SUBQ 0101 DTA 1 SZ EFFADR
Subtract w/ sign extend
SUBX 1001 REG 1 SZ 00 T REG
where REG = 0-7
SZ = 00 = BYTE, 01 = word, 10 = long operations
EFFADR = anything from register to register indirect with index
shorthand for the addressing is
Dn, An, (An), (An)+, -(An), x(An), x(An,xr.s),
x.w, x.l, x(PC), x(PC,xr,s), immediate, status
or condition codes as source or destination
The X86 has instruction, address size, operand size, and segment overide
prefixes that change how the instruction behaves.
The x86 has 14 opcodes for the subtraction
SUB AL, imm8 2C ib
SUB AX, imm16 2D iw <- these depend on the size
SUB EAX,imm32 2D id <- prefix
SUB r/m8,imm8 80
and so forth
Its been a while however I think that the segment in which the code is
running in can affect which instruction is "chosen" and you usually use
the override to change the default behavior. For example if you are in
a 16-bit code region, the override does 32-bits, but in the 32-bit
region the override works on 16-bits.
The VAX has 16 opcodes for subtraction most of which operate on the
D,F,G,H data types. This CPU has variable length instructions in that a
byte is fetched which is the operand and then a "mode" byte. The mode
tells the cpu how many more bytes to fetch in order to complete the
instruction. For example the ADD instruction (ADDL2 - add long 2
operands) which is "C0"
ADDL2 #75,R10 ; add 75 to register 10
the sequence generated is
5a 00 00 00 4b 8f c0 (reading right to left)
whereas
ADDW2 #75,R10 ; add 75 to register 10 (word)
is
5a 00 4b 8f a0
The transputer has only 16 opcodes (it's nibble based) and uses a
special instruction and the "A" register to provide many more (if I
remember correctly 160 more ?). The special instruction tells the
processor to execute the A register.
Back to the question of how it knows, you could design a processor that
the first two bits of the operand tell the processor how long the
instruction is and that if the first two bits are zero, the instruction
is one byte.
So far the base operand is it. x86 = byte, 68K = word, VAX = byte,
transputer = nibble, all the rest of the bytes/words of the instruction
are how the operand access memory and where results go.
confused ? now I am....
Jim