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Re: Another idea for outputting to VGA/DVI/HDMI



On 3/23/2013 9:13 PM, Michael J. Mahon wrote:
Charlie<charlieDOTd@verEYEzon.net>  wrote:
On 3/23/2013 7:01 PM, Sheldon Simms wrote:
On 2013-03-23 20:53:33 +0000, Charlie said:

The problem with any card that uses data from the slot bus is the
inability to synchronize with the Apple video output. This is the way
the Carte Blanche works and I'm pretty sure the Second-Sight card
worked in a similar way (although I've never seen one). The Carte
Blanche output visually is quite good although it doesn't have the
NTSC look. This works well with most video but because of the lack of
synchronization, programs that rely on timing with Vertical Blanking
or interrupting to change palettes, modes, etc. don't do well.

By the way sampling the bus doesn't have to be that fast. The Carte
Blanche does it a 50MHz.

50 Mhz is plenty fast enough, I was just wondering whether the
Beaglebone can do it that fast.

I agree, you probably only need to sample it faster than the Apple writes
it which, of course, is much slower.

Video sync is a solvable problem. Either take the signal where it is
available (IIe slot 7, etc.)

That would probably work with a //e but unfortunately not with a IIgs
because the M2B0 signal is needed for the SHR graphics modes and M2B0 is
not available on slot 7 (and the pin used for it in the other slots is used by CREF).
I may try my hand at soldering a wire to connect the Sync signal to the
Carte Blanche slot just to see how it works.  I can't picture many people
wanting to do this though.

But all Apple II graphics modes use the same VBL signal, don't they?

-michael - NadaNet 3.1 and AppleCrate II: http://home.comcast.net/~mjmahon

Yes they do as far as I know. According to GS technote #40 VBL starts at scan line 192 regardless of the display mode. That is true even with Super HiRes modes. Although that seems strange to me.

What I was getting at is that on a IIgs the Sync (composite horz and vert sync) signal and the M2B0 signal are not both available on any one slot. The M2B0 signal tells the card when bank #1 is being written to on a IIgs. That's critical because Bank #1 holds the SHR video data.

Charlie