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Re: TransWarpGS Clone
On 11/20/2012 02:18 AM, Conrad wrote:
Forgive me if I'm incorrect here as I have never designed an ASIC, only
done FPGA work, but I was under the impression that RTL coding is very
similar between ASIC and FPGA design. There are some different
methodologies used, some things need to be considered for one but not the
other, and sometimes certain aspects of the design need to be changed to
fit a particular FPGA's structure, but there should not be a significant
difference between RTL designed for one and RTL designed for another.
I don't design ASICs either, but I've spent the last 16 years writing
verification software for folks who do and am going by what I've heard from
them.
There are development environments available that will accept RTL and
facilitate it's conversion to either an ASIC or VHDL, or even a bitstream
for a particular FPGA, but they are beyond the reach of hobbyists, at least
if you are buying them legitimately.
Yes, the synthesis, placement and optimisation tools come from folks like
Cadence, Mentor and Synopsys and cost upwards of $20-30k per seat. They are
all heavily protected with software licensing schemes and pirating them would
do you no good at all.
As far as licencing costs of the RTL '816 core from WDC, I'll bet they
want you to buy 10000+ licences at a similar price per license to what
you'd pay per unit buying that many physical chips. There is an opensource
implementation of the '816 instruction set but it's incomplete and I
don't know if it implements the 16-bit side of things or just the 8-bit
part. Once the clone is finished I am going to try and find out what is
involved in licensing the RTL core from WDC and how it all works, but
that's a while off yet.
It would be interesting to know but, yes, one thing at a time :-).