A question to David Empson on ZipGS Cache Memory Speeds

[marvinmiller@hotmail.com (Marvin Miller)]

Hi David !!

Long, long ago in a galaxy far, far away you posted a message relating
to ZipGS memory speeds that I've attached below to 'jog the fog' so to
speak!

Back then, you made a nice table on ZipGS memory speed requirements &
oscillator speeds. I am looking into upgrading my ZipGS and have done
some research on it. Finding these old archives was REALLY useful. I
extrapolated a larger table based on your calculations and am in the
process of getting an order ready for the cache memory chips &
oscillators etc for the ZipGS.

Two Questions;

[1] In light of the time that's gone by (and probably increased
learning) would you say that this table still makes a good 'general'
guide?

[2] If a person bought the fastest possible cache chips (say for a
20Mhz //GS) and than ran the Zip at half that speed (say 10Mhz) would
there be a problem or would it be advantageous to run the processor
Mhz as near as possible to the reccommended chips?

Thanks in Advance David, and I apologize for bringing this thing 'back
from the dead' !

Best;
Marvin Miller

Here's a more complete table based on your long ago theories;


  CPU    Oscillator  ------- DATA RAM speed ----------TAG RAM Speed
 Freq.   Freq. (F)   min (2/F)  max (3/F)  est (2.5/F)     (3/F -30ns)

 7 MHz    28 MHz      71.4 ns     107 ns      89.2 ns     77.1ns
 8 MHz    32 MHz      62.5 ns     93.0 ns     78.1 ns     63.7ns
 9 MHz    36 MHz      55.5 ns     83.0 ns     69.4 ns     53.3ns
10 MHz   40 MHz      50.0 ns     75.0 ns     62.5 ns     45.0ns
11MHz    44 MHz      45.4 ns     68.1ns      56.8 ns     38.1ns
12 MHz   48 MHz      41.6 ns     62.5 ns     52.0 ns     32.5ns
13Mhz     52 MHz     38.4 ns      57.6 ns     48.0 ns     27.6ns
14 MHz   56 MHz     35.7 ns      53.5 ns     44.6 ns     23.5ns
15MHz    60 MHz     33.3 ns      50.0 ns     41.6 ns     20.0ns
16 MHz   64 MHz     31.2 ns      46.8 ns     39.0 ns     16.8ns
17MHz    68 MHz     29.4 ns      44.1 ns     36.7 ns     14.1ns
18MHz    72 MHz     27.7 ns      41.6 ns     34.7 ns     11.6ns
19MHz    76 MHz     26.3 ns      39.4 ns     32.8 ns      9.4ns
20MHz    80 MHz     25.0 ns      37.5 ns     31.2 ns      7.5ns
21MHz    84 MHz     23.8 ns      35.7 ns     29.7 ns      5.7ns
22MHz    88 MHz     22.7 ns      34.0 ns     28.4 ns      4.0ns
23MHz    92 MHz     21.7 ns      32.6 ns     27.1 ns      2.6ns
24MHz    96 MHz     20.8 ns      31.2 ns     26.0 ns      1.2ns
25MHz   100MHz     20.0 ns      30.0 ns     25.0 ns      0.0ns



****Original Message from Aug '97******

Newsgroups: comp.sys.apple2
Subject: Re: IIgs Zip accelerator SRAM speeds
From: dempson@actrix.gen.nz (David Empson)
Date: Wed, 27 Aug 1997 23:03:43 +1200
Message-ID: <19970827230343817275@dempson.actrix.gen.nz>
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Stephen McGrogan <smcgroga@gandalf.Advent.COM> wrote:

> My question is, if 65ns SRAMs work at 7-8 mhz (28-32mhz oscillators),
> why do I need 15ns SRAMs to run at 12-15mhz (48-60mhz oscillator)?
> What is the actual relationship between the SRAM speed and the
> oscillator clock speed?

I don't think anyone has ever described a clear relationship between
the clock frequency and required cache RAM speed.  The following is my
current theory on how it might work.  I make no claims that this
theory is correct!

In general, the speed of the TAG RAMs is more important than the speed
of the DATA RAMs.  The DATA RAMs need to be fast enough to complete an
access in about half to three quarters of a CPU cycle, thus the
required speed is somewhere between (2 / F) and (3 / F) where F is the
oscillator frequency.

The TAG RAM may need to be faster than this.  I don't know exactly how
the ZIP implements its tag mechanism, but it needs at least two pieces
of information for each DATA byte:

1. Is this byte valid?
2. Which bank does this byte come from?

The first item could be implemented by reserving an illegal bank
number (e.g. $EF).

If the ZIP has less than 64K of cache, it also needs to know the top
one or two bits of the address within the bank.  This means that it
needs more than one byte associated with each data location.  This
could be handled by sharing tag locations between two data bytes, but
this would mean the tag RAM has to be read twice.

I suspect that the ASIC has a small amount of RAM internally, which is
used to hold the extra tag information if there is less than 64K of
cache.  It would need 32768 bits (two bits for each location in a 16K
cache), which is only 4096 bytes - not too large to fit inside an
ASIC.

Given these assumptions, the ASIC could handle the cache by
simultaneously reading the TAG and DATA locations, and deciding
whether a main memory read is required as soon as the TAG information
is available.  The DATA information might not be needed as quickly.

The ASIC has to wait until the CPU has generated the address (about a
quarter of the way through the cycle) before it can address the cache.
It can use the VPA and VDA signals to identify when the address is
ready.  The decision about whether the right location is in the cache
is probably synchronized to the oscillator (4 times the CPU cycle), so
I expect the TAG RAM would have to be able to complete an access
within half a cycle (assuming the decision about using the cache is
made at the 3/4 point in the CPU cycle).

For a cache hit, the DATA RAM is already outputting the appropriate
value, and it will be ready by the end of the cycle.

For a cache miss, the ZIP needs to synchronize with the clock speed of
the main computer.  This is the really tricky bit that I haven't
thought through yet.

If the ZIP wants to improve the average synchronization time, it could
require the TAG RAM to be twice as fast as the DATA RAM, but this
doesn't appear to be the case (from observation of shipped ZIPs at
speeds from 7 MHz to 9 MHz).

Now for the explanation of why you need faster TAG RAM at higher
speeds: there are probably delays introduced by discrete logic and/or
the ASIC itself, which use up a constant amount of time.  At lower
frequencies this isn't significant, but as the clock frequency
increases you need substantially faster TAG RAM to compensate for this
fixed delay.

Another factor is that the TAG information is probably needed earlier
in the cycle than the DATA.

Assuming my theories are correct, the required speed range of the DATA
RAM is somewhere between the following limits:

  CPU    Oscillator  ------- DATA RAM speed ----------
 Freq.   Freq. (F)   min (2/F)  max (3/F)  est (2.5/F)
 7 MHz    28 MHz      71 ns     107 ns      89 ns
 8 MHz    32 MHz      62 ns      93 ns      78 ns
 9 MHz    36 MHz      55 ns      83 ns      69 ns
10 MHz    40 MHz      50 ns      75 ns      62 ns
12 MHz    48 MHz      41 ns      62 ns      52 ns
14 MHz    56 MHz      35 ns      53 ns      44 ns
16 MHz    64 MHz      31 ns      46 ns      39 ns