Re: Apple II Bus Timing

[Patrick Schaefer <patrick.schaefer@topmail.de>]

Andrew Quinn schrieb:

> The apple bus provides o0 (rather than o2) for bus timing and this appears
> to lead o2 due in the timing diagrams but I cannot find timing details of
> this lead so I can hold the data on the bus a little longer.

phi0 is the clock signal that drives the 6502, Apple's phi1 is its
complement. From this phi0 the 6502 derives phi1 (the real one, not
Apple's) and phi2, to which its timing is related. Apple phi0 leads 6502
phi2 by a few ns. 

The /Device_select and /IO_select signal become active with Apple phi0,
this can be used to drive 74LS373 D-latches as outputs and 72LS245
buffes as inputs. 

To generate a 6502 phi2 signal to drive 6522 VIAS, 6581 SIDs or things
like that, invert phi0 and NOR it with Q3. This can be done using 1/2
74LS02, one as an inverter and one as a NOR. The resulting singal is not
symmetric, but it works.

For a quick and dirty implementation of an IDE interface, look at
http://home.freeuk.net/c.ward/6502/schematics/ide.gif
However, to make it fast, you will need DMA. And to make it really fast,
you will need some kind of burst DMA with 2..3 transfers in one cycle
(like the Z80 Softcard does).


Patrick