Re: Applesoft I and II and floating-point performance

[pausch@saafNOSPAM.se (Paul Schlyter)]

In article <processoroverclocked-1505002042340001@nn-157-22-180-111.napanet.net>,
 
> In article <20000515031428.01786.00002501@ng-fl1.aol.com>, mjmahon@aol.com
> (Michael J. Mahon) wrote:
> 
>> Paul Schlyter replied:
>> 
>>>...
>>>In the 80188 the integer multiply was implemented in
>>>hardware instead, resulting in a speedup of a factor of about 3: now
>>>it required only some 30 clock cycles.
>> 
>> If it takes more than 3 cycles for an integer multiply,
>> then it's not hardware--it's still microcode.
> 
> JSR and RTS are 6 cycles. They are less complex than an integer multiply.
> Are you saying a JSR is microcode?
 
On the 6502 it may very well be -- remember that the 6502 had fewer
transistors than most contemporary 8-but CPU's.  And the purpose of
microcode is to keep the transistor count down.
 
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