Re: Super GS Project (Update for Accelerator)

[Frank Carney <frankc@srv.net>]

Sheane and Bonnie Meikle wrote:
> 
> Ok now that Sequential Systems has announced that they will be releasing the
> schematics and code for their products on their web page and we have a basic
> idea of what we are wanting to include in the prototype we need people to
> help design the new system. We need to get this project going or it'll end
> up dying just like all the other times this idea has come up. DON'T let the
> dream die.
> 
> Sheane
> 
> Apple II Forever
> http://www.insidetheweb.com/mbs.cgi/mb996045
> --


I got my wire wrap version up and running, but ran into some terrible
noise problems.  I am rebuilding the circuit with point to point wiring
to "hopefully" reduce the noise problems.  I also have been looking into
the 386 version and what it will take to build.  It looks as though it
may be simpler to build a variable speed 386 accelerator easier than an
8088 version.  As soon as I tackle the noise problems and get a decent
interface to the IIgs designed I will start building the 386 version. 
Or I may start sooner, who knows?  The 386 seems to need less support
chips as far as clock and buffer chips.  It also allows a the data bus
to dynamically be set to 16 or 32 bit data bus.  If I am only addressing
a small area of memory (1 Meg) I can significantly reduce the complexity
of the system.  I do not have to worry about protected mode and still
get the awesome 32 registers and it will still work with the program
written for the 8088 to boot!

Anyway, someone IS working on this stuff even if it only is the
accelerator.  Note: I did play around a little with placing a 486 baby
AT MB in the IIgs.  If you remove the power supply and provide cards
that can plug in sideway to the case then you should be able to design a
Super GS in the original case!  This would be a pain to work on, but hey
what is the point of doing it if it is not hard!

	Hard at work,
	Frank