Re: VHDL for use in accelerator?

[Frank Carney <frankc@cyberhighway.net>]

bobryan9@my-deja.com wrote:

> Interesting idea.  How much do VHDL chips cost?  A friend
> of mine does VHDL programming, and the chips that he is
> currently working with are at least $100.  He is using
> reprogrammable VHDL chips.
>
> From what I understand about these chips, you should be
> able to program one with the necessary parts of a 6502
> or 65816 chip, with the cache and timing components
> necessary to interface with the Apple bus.  You might
> even be able to put the cache on the chip (I don't
> know if VHDL's are available with RAM integrated, or if
> you could program them to include RAM.)
>
> This could be the route to developing and producing "low
> cost", 'easy' to build accelerators for the IIgs and IIe.
> You can take care of alot of the hardware with the VHDL,
> and eliminate the cost of doing so much hardware prototyping.
>
> VHDL, RAM chips for cache, power supply.
>
> This seems like a practical application of the 65XX VHDL.  I
> don't see why you would want a processor VHDL by itself.  Why
> not just go buy a 50 cent 6502?
>
> Bob
>
> In article <388B7776.3891B5F3@cyberhighway.net>,
>   Frank Carney <frankc@cyberhighway.net> wrote:
> > Could that VHDL image be used to create a single chip or close to
> single
> > chip accelerator?
> >
> > The main 6502 processor could be coupled with additional logic to
> access
> > cache and provide the correct timing to the motherboard.
> >
> > Is this doable or am I just talking out my XXX?
> >
> > If it is doable then maybe a 65816 VHDL image would be great for the
> > IIGS.
> >
> >
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

I have 6502s.  I thought it might be a good idea for an accelerator
application as you have already stated.  I guess I am confused about
something.  I thought VHDL was a language to describe the logic.  Did I
miss something?  I was thinking of using a FPGA chip using VHDL to design
the logic for an accelerater.  As you also stated the timing could be
taken care of and any "glue" could be put on the FPGA.  I think the cache
may be able to be on the FPGA if the registers can be.  This would
provide for an L1 cache and an additional L2 cache could be added outside
if needed.  Now that I think about it this may be a cool project to get
some experience with!

Alas, cache...er...cash flow would be a limiting factor if the FPGA chips
and programmers are expensive.