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Re: Carte Blanche Atto (CB for the IIc)

Subject: Re: Carte Blanche Atto (CB for the IIc)
From: "Bill Garber" <willy46pa@garberstreet.com>
Date: Mon, 28 Mar 2011 12:40:14 -0400
Newsgroups: comp.sys.apple2
References: <7b838439-9cc7-46ec-950d-6255b549ae35@r4g2000prm.googlegroups.com> <Yq2dnT-HBr7z5w3QnZ2dnUVZ_h2dnZ2d@giganews.com> <33c82f42-feee-4f7c-a1db-7e5062ca543d@t19g2000prd.googlegroups.com> <8db25c65-774e-4828-8738-7213a51bb18a@k3g2000prl.googlegroups.com>
Reply-to: "Bill Garber" <willy46pa@garberstreet.com>
Xref: g2news2.google.com comp.sys.apple2:22991

"rich12345" <aiiadict@gmail.com> wrote in message news:8db25c
65-774e-4828-8738-7213a51bb18a@k3g2000prl.googlegroups.com...
On Mar 28, 5:26 am, a2retro <a2retrosyst...@gmail.com> wrote:
>> In order to use that information you need to make a UCF file
>> (pin to signal map file) or ask someone who has already made
>> one to give you a copy.
>
> UCF for CB is available on the net somewhere... I have a copy.
> It tells you what pin on FPGA goes to which pins on:  Apple II
> slot connector, IDE connector, video connector, etc.

Here is the CB.UCF file:

#NET "SDO"   LOC = "P87" | IOSTANDARD = LVCMOS33 ;
#NET "SDI"   LOC = "P61" | IOSTANDARD = LVCMOS33 ;
#NET "SCL"   LOC = "P103" | IOSTANDARD = LVCMOS33 ;
#
# SPI devices
#
#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "BUS_3M58"  LOC = "P51" | IOSTANDARD = LVCMOS33 ;
NET "BUS_7M"  LOC = "P80" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<0>"  LOC = "P4" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<10>"  LOC = "P36" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<11>"  LOC = "P39" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<12>"  LOC = "P40" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<13>"  LOC = "P47" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<14>"  LOC = "P48" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<15>"  LOC = "P49" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<1>"  LOC = "P8" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<2>"  LOC = "P11" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<3>"  LOC = "P9" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<4>"  LOC = "P12" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<5>"  LOC = "P31" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<6>"  LOC = "P33" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<7>"  LOC = "P30" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<8>"  LOC = "P23" | IOSTANDARD = LVCMOS33 ;
NET "BUS_A<9>"  LOC = "P22" | IOSTANDARD = LVCMOS33 ;
NET "BUS_D<0>"  LOC = "P3" | IOSTANDARD = LVCMOS33 ;
NET "BUS_D<1>"  LOC = "P5" | IOSTANDARD = LVCMOS33 ;
NET "BUS_D<2>"  LOC = "P16" | IOSTANDARD = LVCMOS33 ;
NET "BUS_D<3>"  LOC = "P19" | IOSTANDARD = LVCMOS33 ;
NET "BUS_D<4>"  LOC = "P18" | IOSTANDARD = LVCMOS33 ;
NET "BUS_D<5>"  LOC = "P29" | IOSTANDARD = LVCMOS33 ;
NET "BUS_D<6>"  LOC = "P24" | IOSTANDARD = LVCMOS33 ;
NET "BUS_D<7>"  LOC = "P35" | IOSTANDARD = LVCMOS33 ;
NET "BUS_DMA"  LOC = "P41" | IOSTANDARD = LVCMOS33 ;
NET "BUS_DMAIN"  LOC = "P72" | IOSTANDARD = LVCMOS33 ;
NET "BUS_DMAOUT"  LOC = "P69" | IOSTANDARD = LVCMOS33 ;
NET "BUS_INH"  LOC = "P45" | IOSTANDARD = LVCMOS33 ;
NET "BUS_INTIN"  LOC = "P71" | IOSTANDARD = LVCMOS33 ;
NET "BUS_INTOUT"  LOC = "P68" | IOSTANDARD = LVCMOS33 ;
NET "BUS_IOSTROBE"  LOC = "P54" | IOSTANDARD = LVCMOS33 ;
NET "BUS_IRQ"  LOC = "P63" | IOSTANDARD = LVCMOS33 ;
NET "BUS_NMI"  LOC = "P65" | IOSTANDARD = LVCMOS33 ;
NET "BUS_PHASE0"  LOC = "P20" | IOSTANDARD = LVCMOS33 ;
NET "BUS_PHASE1"  LOC = "P26" | IOSTANDARD = LVCMOS33 ;
NET "BUS_Q3"  LOC = "P43" | IOSTANDARD = LVCMOS33 ;
NET "BUS_R_W"  LOC = "P50" | IOSTANDARD = LVCMOS33 ;
NET "BUS_RDY"  LOC = "P42" | IOSTANDARD = LVCMOS33 ;
NET "BUS_RESET"  LOC = "P60" | IOSTANDARD = LVCMOS33  | PULLUP ;
NET "BUS_SYNC"  LOC = "P57" | IOSTANDARD = LVCMOS33 ;
NET "BUS_USER1"  LOC = "P32" | IOSTANDARD = LVCMOS33 ;
NET "h_sync"  LOC = "P89" | IOSTANDARD = LVCMOS33 ;
NET "IDE_ACT"  LOC = "P189" | IOSTANDARD = LVCMOS33  | DRIVE = 2 ;
NET "IDE_CS1"  LOC = "P187" | IOSTANDARD = LVCMOS33 ;
NET "IDE_D<0>"  LOC = "P93" | IOSTANDARD = LVCMOS33 ;
NET "IDE_D<1>"  LOC = "P78" | IOSTANDARD = LVCMOS33 ;
NET "IDE_D<2>"  LOC = "P167" | IOSTANDARD = LVCMOS33 ;
NET "IDE_D<3>"  LOC = "P165" | IOSTANDARD = LVCMOS33 ;
NET "IDE_D<4>"  LOC = "P164" | IOSTANDARD = LVCMOS33 ;
NET "IDE_D<5>"  LOC = "P168" | IOSTANDARD = LVCMOS33 ;
NET "IDE_D<6>"  LOC = "P147" | IOSTANDARD = LVCMOS33 ;
NET "IDE_D<7>"  LOC = "P133" | IOSTANDARD = LVCMOS33 ;
NET "IDE_RES"  LOC = "P153" | IOSTANDARD = LVCMOS33  | PULLUP;
NET "N_BUS_DEV_SEL"  LOC = "P14" | IOSTANDARD = LVCMOS33 ;
NET "N_BUS_IO_SEL"  LOC = "P204" | IOSTANDARD = LVCMOS33 ;
NET "RGB<0>"  LOC = "P145" | IOSTANDARD = LVCMOS33 ;
NET "RGB<1>"  LOC = "P146" | IOSTANDARD = LVCMOS33 ;
NET "RGB<2>"  LOC = "P140" | IOSTANDARD = LVCMOS33 ;
NET "RGB<3>"  LOC = "P144" | IOSTANDARD = LVCMOS33 ;
NET "RGB<4>"  LOC = "P83" | IOSTANDARD = LVCMOS33 ;
NET "RGB<5>"  LOC = "P150" | IOSTANDARD = LVCMOS33 ;
NET "SD_CS"  LOC = "P62" | IOSTANDARD = LVCMOS33 ;
NET "SD_DET"  LOC = "P58" | IOSTANDARD = LVCMOS33 ;
NET "SOFT_TCK"  LOC = "P184" | IOSTANDARD = LVCMOS33 ;
NET "SOFT_TDI"  LOC = "P159" | IOSTANDARD = LVCMOS33 ;
NET "SOFT_TDO"  LOC = "P113" | IOSTANDARD = LVCMOS33 ;
NET "SOFT_TMS"  LOC = "P154" | IOSTANDARD = LVCMOS33 ;
NET "spi_rom_cs"  LOC = "P55" | IOSTANDARD = LVCMOS33 ;
NET "spi_sck"  LOC = "P103" | IOSTANDARD = LVCMOS33 ;
NET "spi_sdi"  LOC = "P61" | IOSTANDARD = LVCMOS33 ;
NET "spi_sdo"  LOC = "P87" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<0>"  LOC = "P206" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<10>"  LOC = "P100" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<11>"  LOC = "P102" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<12>"  LOC = "P99" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<13>"  LOC = "P134" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<14>"  LOC = "P135" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<15>"  LOC = "P138" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<16>"  LOC = "P137" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<1>"  LOC = "P126" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<2>"  LOC = "P123" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<3>"  LOC = "P122" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<4>"  LOC = "P179" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<5>"  LOC = "P84" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<6>"  LOC = "P86" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<7>"  LOC = "P197" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<8>"  LOC = "P196" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_A<9>"  LOC = "P186" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_D<0>"  LOC = "P116" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_D<1>"  LOC = "P163" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_D<2>"  LOC = "P171" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_D<3>"  LOC = "P90" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_D<4>"  LOC = "P76" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_D<5>"  LOC = "P120" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_D<6>"  LOC = "P97" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_D<7>"  LOC = "P129" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_NCS0"  LOC = "P161" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_NCS1"  LOC = "P119" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_NOE"  LOC = "P127" | IOSTANDARD = LVCMOS33 ;
NET "SRAM_NWE"  LOC = "P94" | IOSTANDARD = LVCMOS33 ;
NET "SYSCLK"  LOC = "P183" | IOSTANDARD = LVCMOS33 ;
NET "v_sync"  LOC = "P77" | IOSTANDARD = LVCMOS33 ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Followed by the Clock() add-on. These get inserted
into the above file as necessary:

# Generated by Xilinx Architecture Wizard
# --- UCF Template Only ---
# Cut and paste these attributes into the project's UCF file, if desired
INST DCM_SP_INST CLK_FEEDBACK = 1X;
INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
INST DCM_SP_INST CLKFX_DIVIDE = 7;
INST DCM_SP_INST CLKFX_MULTIPLY = 25;
INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
INST DCM_SP_INST CLKIN_PERIOD = 69.541;
INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
INST DCM_SP_INST FACTORY_JF = C080;
INST DCM_SP_INST PHASE_SHIFT = 0;
INST DCM_SP_INST STARTUP_WAIT = FALSE;

References:
- Carte Blanche Atto (CB for the IIc)
  - From: Steve <srkh28@gmail.com>
- Re: Carte Blanche Atto (CB for the IIc)
  - From: Steven Hirsch <snhirsch@gmail.com>
- Re: Carte Blanche Atto (CB for the IIc)
  - From: a2retro <a2retrosystems@gmail.com>
- Re: Carte Blanche Atto (CB for the IIc)
  - From: rich12345 <aiiadict@gmail.com>

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