Re: Apple2 disk controller questions

[dempson@actrix.gen.nz (David Empson)]

Fabrice Frances <frances@ensica.NOSPAM.fr> wrote:

> Now I understand my error !  I was counting 250x1024 bps
> as the transfer rate instead of 250000bps...

Well, on further reflection, this number isn't quite right.

The master clock which drives the IWM (and all derivatives) on a US
machine is 14.31818 MHz, so the bit cell time used by the IWM on a 5.25"
drive is actually (4 * 14/14.31818) = 3.911 microseconds

This means that the actual data rate is 255689 bits per second.

> Poor me, I have assumed this 256000 bps for several years,

That is actually closer than 250000.  Once you factor in the rotation
speed, the number of bits per track is about 51137.

This is still within the upper limit for all the gaps (53184 bits per
track), and the .nib format's 6656 nibbles per track is sufficient to
cover the minor increase.

Incidentally, the PAL version of the IIe and IIc uses a slightly slower
clock frequency, so the bits are marginally longer than for a US IIe,
and there are therefore slightly fewer bits per track.

> I should have asked myself where the clock for
> such a rate is... (the 'Mega' on those 8Mhz crystals is
> surely not the same as on those hard drives ;-)

The Apple II doesn't use an 8 Mhz clock source for the IWM.  The Mac
does, but even then it isn't 8 MHz (I don't know what the actual figure
is off the toof my head).

> Ok, so this means 6250 bytes per track for a MFM...
> (your 7250 theoretical limit is a typo, isn't it ?)

Assuming 50000 raw FM data/clock bits per track, you could get 50000 MFM
data bits per track (with no sectoring overhead).  Divide by 8 is 6250.
Yep, must have been a typo.

> In fact, 50000 bits can be used on a track, whatever the
> encoding format is, am I right ?

(Note that a "1" bit is a field reversal, and a "0" bit is no change in
the field.  FM and MFM clock bits are always "1".  GCR doesn't have
clock bits.)

FM could only store 25000 data bits on the track, since you have to
alternate clock and data bits.  There would be 50000 raw bits in total:
25000 would be 1 (clock), and the rest could be either 1 or 0.

GCR could store about 37500 data bits (6-and-2 encoding), which again is
50000 raw bits in total, with various numbers of 1 and 0 bits according
to the data pattern.

I'm not sure what actual number of bits would be stored for MFM.  It
would depend on the pattern.  If the entire track was full of one bits,
or the entire track was full of zero bits, then you would have 50000 raw
bits (and no way to decode the data!) - data bits in the case of
1111..., clock bits in the case of 0000....

If you had an alternating 101010... pattern, then no clock bits would be
required.  A 100100... pattern would require a clock bit in the middle
of each pair of zero bits.

> So, I'm still wondering why those .nib images hold 6656 bytes...
> I can see two reasons, could you help ?
> - the rate is 255kbps instead of 250kbps, as David Wilson states
> in his table... can anyone look into an Apple2 controller and read
> the crystal frequency in order to be sure ?

See above.  There is no crystal on the controller card anyway - it uses
the motherboard 7M clock (14.31818 MHz divided by 2), and some of the
derived clocks, which are slightly irregular multiples of the 7M clock
period.

The main CPU and video phase 0 and phase 1 clocks run at a nominal 1
MHz: they are toggled every 7 half-cycles of 7M.  In a US IIe, there is
also an irregular addition of one 7M cycle every 65th CPU cycle (to
correct NTSC video timing).

There is also the Q3 clock, which runs at a nominal 2 MHz: it is toggled
every 4 then 3 half-cycles of 7M (high period is longer than low
period).  It is in sync with Phi0 and Phi1, so it must be stretched in
the same way.

Since the 5.25" write has to stay in sync with the CPU clock, the disk
controller must be locked to any of Q3, Phi0 or Phi1, and it needs 7M
for faster internal timing operations.

I can't find my DOS 3.2 reference manual just at the moment (which has a
circuit diagram of the Disk ][ controller), but looking at the IIgs
circuit diagram, I see that the IWM chip uses 7M and Q3.

-- 
David Empson
dempson@actrix.gen.nz
Snail mail: P.O. Box 27-103, Wellington, New Zealand