Re: What's the IIe's--Arghh!--MHz Speed?

[david@uow.edu.au (David Wilson)]

kloesch@nauticom.net (Kevin Loesch) writes:
>        All 6502 chips require at least two cycles per instruction, one for 
>the execution and on to fetch the next instruction. The 65816 could prcocess 
>an instruction in one cycle since it was a pipelined processor(As long as the 
>current instruction wasn't a branch or jump). 

The 6502 is pipelined. Instructions take more than two cycles but some are
overlapped. Fetch, Decode, Execute. The next fetch takes place during the
execute of the previous instruction.

I do not recall seeing any 1 cycle instructions on the 65816. It certainly
shaved a cycle off many 3+ instructions.
--
David Wilson  School of IT & CS, Uni of Wollongong, Australia  david@uow.edu.au