Re: Need help with Zip-- RAMS and stuff

[Rubywand <rubywand@swbell.net>]

pubpc1@library.ucla.edu wrote:
> 
> JB wrote:
> >
> > Can anyone give me an idea as to why my Zip (version 1.02) will crash my
> > system when I have the dip switches set to recognize 32 or 64k cache?
> > When I have it set to only recognize 16 it works just fine.
> >
> > When it crashes it drops out of the GS/OS into some garbled text on my screen.
> >
> > Any help is appreciated.
> >
> > thanks!
> 
> Hmm...JB, it sounds like my Zip GS at 13.75MHz.  I have 64K
> of cache installed, but I have to leave it set at 16K to make
> it stable.  It depends on your 65C816 chip, the speed of the
> SRAMs, and your particular GS.
>

     This info may be helpful: The standard, from-the-factory Zip-GSx
10Mhz/64k board uses Motorola MCM6206P45 (45ns) 32kx8 static RAM chips
for both Data and Tag RAM. The two 74xxx IC's are Fairchild "FAST" 74Fxx
series (74F00 and 74F02) IC's.
 


> Did you install a new 14MHz 65C816 from Alltech or WDC?  This
> is needed to go above 10MHz.  You might be able to get the
> older chip to go to about 10MHz with just an oscillator swap,
> but this may require lowering cache size setting, as you've
> discovered.  Next, what is the speed of your SRAMs?  If they
> are 70ns in all four sockets labelled HM62256LP-70 or similar,
> you should be able to set 64K.  If there are two of these
> chips, you can only set 32K.
> 
> If you have 70ns chips in DATA, but 15ns in TAG, then your
> Zip should be able to break 10MHz to the higher speeds. ....

     Probably, but, the user is going to be cutting it kind of close on
Data RAM speed for anything much more than 10MHz, especially for more
than 16k cache.
 
     Evidently, the explanation for problems with expanding cache relate
to delays introduced by additional decoding. My guess is that flipping
the DIP switches probably sets Chip Enable decoding through the 74xxx
gates. The delays, supposedly about 5ns/gate for 74Fxx, mean that the
extra RAM has to be faster because it has less time to react to Enable. 

     At 13.75MHz, you are pushing the rated speed for 70ns RAM with no
decoding delays figured in. If two FAST gate delays are involved for 32k
or 64k, you would need 50ns Data RAM. At 12.5MHz, you gain about 8ns of
breathing space, but, still not enough to expect dependable operation if
two gate delays are needed to select the extra cache.


     Most likely, the explanation for needing faster Tag RAM relates to
decoding delays through the Zip IC. 15ns may be over-kill, but, for sure
it avoids speed problems.
        


Rubywand