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New csa2 FAQs: F002ACCEL (Part 1 of 2)
Apple II Accelerators
Csa2 FAQs-on-Ground file: FxxxAccel.txt
This material compiled by the Ground Apple II site, 1997.
It may be freely distributed.
Note: This is a pure Text file which has no Font, Color, etc.
formatting. To correctly view tables and diagrams on a super-res
display, use a mono-spaced Font such as CoPilot or PCMononspaced.
____________________________
001- What are the correct settings for a ZipGS?
002- Why should Appletalk Delay be disabled with a ZipGS?
003- How do I set up a Transwarp on my IIe?
004- Is there a way of disabling Transwarp for games?
005- What are specs & jumper settings for a vintage SpeedDemon?
006- How does the SpeeDemon rate as an accelerator?
007- My SpeeDemon accelerator board seems to run hot. A fix?
008- How should the DIP switches be set on a v3.03 SpeedDemon?
009- How can I get a 'Cache Hit' indicator for my ZipGS?
010- How can I program the ZipGS registers?
011- Is there some ZipGS mod that will improve performance?
012- I have a 7MHz ZipGS. How fast can the board be pushed?
013- Now that faster 65C816's are available, can I upgrade?
014- How do I do the 14 MHz ZipGS upgrade?
015- What GALs version do I need to speed up my TWGS?
016- Where can I get the correct GALs?
017- What Oscillator freq corresponds to what speed?
018- What kind and speed of static cache RAMs do I need?
019- Is it really necessary to increase board voltage
020- What kind of performance increase can I expect?
021- How do I change from 5v to 5.25v
022- Why are my ZipGS settings via the Zip CDA forgotten?
023- What do the check-marks mean in the ZipGS CDA?
024- Why don't my ZipGS settings match DIP switch settings!?
From: Marc Sira
001- What are the correct settings for a ZipGSx? I've tinkered
with "CPS Follow", "Counter Delay" and the like but have
no idea what I'm actually doing.
CPS Follow should always be enabled. If you disable it you will have
problems with Disk ]['s and System 6's AppleTalk driver and anything
else that expects the Zip to slow down to 1 mhz when the GS is
instructed to slow down to 1mhz. For instance, border text demos (like
the FTA XMAS demo) won't work if you have this disabled. Expect weird
things to happen if you play with this one.
Counter Delay I would recommend leaving enabled. This causes the Zip to
"deaccelerate" (actually all it does is temporarily ignore that any data
can be read from the cache instead of the motherboard) for about 5
milliseconds any time you read one of the Video Counters -- this is
really only there so that one of the self-tests will pass. Which way you
set it shouldn't be fatal.
AppleTalk or Interrupt Delay should always be disabled. The desktop will
run much slower if you enable it. The only reason most people needed it
was for AppleTalk under system 5, and I have an init on tybalt that
fixes that. System 6 fixed the problem but requires CPS Follow to be
enabled for the fix to work.
Speaker and Paddle delays are intended to let old 1-bit sounds and
Paddle access work the way they do on an unaccelerated IIgs. I recommend
leaving these on unless you feel like experimenting. They shouldn't be
fatal but some program might react very negatively, so be prepared.
Bank C/D cache enable -- leave this at the default setting and forget
about it. This tells the Zip if it's OK to cache bank-switched RAM (the
old language card area). Zip's own docs say "there is no know software
requiring this" but that it why it's there, in case somebody ever finds
software that doesn't like it you can try setting it the other way.
____________________________
From: Todd P. Whitesel
002- Why should Appletalk Delay be disabled with a ZipGS?
Because it saps performance every time an interrupt occurs.
The Appletalk delay was originally called the "Interrupt Delay" but they
renamed it at the last minute because somebody actually tried an 8/64 on
an Appleshare network and it dropped packets like crazy.
With "Appletalk delay" on, every time an interrupt occurs your Zip will
disable acceleration for 5 ms, just like it does with the paddles and
the speaker and the others. This is a significant effect because with
VBL interrupts going you have one every 16 ms, so your Zip spends nearly
1/3 of the time not accelerating you.
Why this "fixes" appletalk: in system 5 and earlier (including the ROM
appletalk code), there are software timing loops which assume 2.8 mhz
operation. As you speed the system up, it gets more and more likely to
drop incoming packets because it thinks they are being sent too slowly
to be correct, when in reality the appletalk code is timing out too
fast.
Why the Appletalk delay is not a complete solution: a full-size
Appletalk packet that you'd get from a file server takes about 14 ms to
transmit. The Appletalk delay covers the first 1/3 of the packet, the
VBL interrupt covers at most another third of the packet, but nothing is
guaranteed to keep acceleration off for the whole packet. If you speed
the Zip up more, say to 10/64, it starts dropping long packets no matter
what.
This latter problem was why I originally wrote ZipTalk. It required a
slot delay to be enabled (in, say, slot 6 or 7), and before each
appletalk packet was received I tweaked that slot -- slot delays are 50
ms, so the Zip stays unaccelerated way past the end of the packet and
everything works. (I also patched packet sending, to be safe.)
In system 6 Apple fixed things correctly in the appletalk drivers. I
removed the code from ZipTalk and released what remained as ZipFix. As
of 6.0.1, the cursor flicker problem was fixed by apple in the control
panel, so now you only need ZipFix for the GS/OS SET_SYS_SPEED hook,
which nobody seems to use.
______________________________
From: Jeff Brielmaier
003- How do I set up a Transwarp on my IIe?
Bank1: Sw 1-7 -> Change to OPEN if there is a memory card that uses the
"Langauge Card bank switching technique". (Normally CLOSED)
Bank1: Sw 1-7 -> Change to OPEN if the plug in card must be accessed at
1 MHz (Normally CLOSED. OPEN for Floppy diskette controllers)
Switch 8 on both Banks: Sets the power up speed of Transwarp
Bank1 Bank2
3.6 MHz OPEN OPEN <<Normal>>
1.7 MHz CLOSED OPEN
1 MHz OPEN CLOSED
1 MHz CLOSED CLOSED
----------------------
004- Is there a way of disabling Transwarp for games?
Press <Esc> at power-up will disable Transwarp completely until the next
power off/on cycle.
A better way is to write a 01 to $C074. This will slow Transwarp down
to 1 MHz without disabling it completely. Writing a 00 to $C074 will
restore Transwarp to it's 'fast' speed.
____________________________
From: Rubywand
005- I recently bought an "M-c-T SpeedDemon" board. It's dated 1984
and draws a small apple on the screen after power-up. What kind
of cache RAM does it have? There's a place for jumpers near the
top of the card. Is there a way to control this thing through
software or hardware?
The RAMs on our Speedemon are 100ns 2048x8 9128's (for a total 8K
of pretty speedy cache).
I once asked McT about the jumper block you mention, they said the
jumper is set at the factory to adjust on-card timing and to Leave It
Alone. (On our card, the jumper block has 5 pairs. The pair 2nd from the
top is jumpered.)
There is also a jumper pair near the bottom middle of the card.
This is the Speed Jumper. Jumper it if you want 'demon to slow down for
I/O accesses to Slots 4 & 5. (The 'demon always slows for Slot 6 I/O
($C0E0 - $C0EF.)
According to the "Manual" (a folded card), pressing PDL-1
(Closed-Apple on a IIe) upon power-up will engage a self-test. Pressing
ESC at power-up will turn OFF the card and allow running at normal
speed. To turn OFF the card later on, do a POKE (49152+256*S) where S=
Slot # of the slot the card is in; then, press RESET.
You can put the 'demon into any Slot; but, if you put it in Slot 0
(Slot 3 in a IIe), the card will not respond to any KB shut-off
commands.
Your card may be a slightly later model. (I've never noticed ours
draw a hires apple on the screen-- darn it!) Possibly, McT came out
with a revision aimed at 128K IIe's.
------------------------
006- How does the SpeeDemon rate as an accelerator for II+
and IIe Apples?
In terms of raw performance (once you arrange for cooling),
SpeeDemon may be the best of the 4MHz accelerators for early II's. I've
never noticed any compatibility problems and the approx. X3.5 speed
increase puts real 'snap' into your machine's response. (Besides, it's
great for games like Elite!)
------------------------
007- My SpeeDemon accelerator board seems to run hot in my II+.
Is this normal? Should I add cooling?
Indeed, the 'demon is a power gobbler-- roughly 1.5A as I recall--
and some of the IC's run hot. When the board bombed after one long
session, we cut out a square section on the back of the II+ and added a
mini-fan, just to blow air across the 'Demon board. This ended the heat
problem.
____________________________
From: Douglas M. Howell
008- How should the DIP switches be set on a version 3.03
SpeeDemon board?
This is from the 1-page manual that comes with the card:
For owners without a Bank Switch Language Card in thire Apple, the
first seven DIP switches control the access speed of the following:
switch 1 -- controls -- slot 1
switch 2 -- " -- slot 2
switch 3 -- " -- slot 3
switch 4 -- " -- paddle/joystick port
switch 5 -- " -- slot 5
switch 6 -- " -- slot 6
switch 7 -- " -- slot 7
OFF indicates slot/port is accessed at High Speed.
ON indicates slot/port is to Slow Down for access.
All slots that can be accessed at High Speed and all empty slots
should have the corresponding Dip switch set to "OFF" (this is the
non-bank switch setting).
Special Note about Switch 4:
Switch 4 on the SpeeDemon DIP switch no longer controlsthe access
speed to slot 4. It now controls how the joystick and paddles are read.
If switch 4 is in the "ON" position, the SpeeDemon will slow down
to normal Apple speed for 50 milliseconds each time the joystick is
accessed. This allows the software to read the joystick or paddles
correctly. If switch 4 is in the "OFF" position, the SpeeDemon will not
slow down when they are accessed.
Access to slot 4 is always at SLOW (normal) Apple speed.
Certain programs, such as Appleworks, use the joystick location,
even when the joystick is not in use. If dip switch 4 is set to "ON"
then these programs will not show any speed for some functions, such as
calculations and sorts. Therefor, unless you need youysticks for your
applications, switch 4 should be set in the "OFF" position.
If you have a Bank Switch Card (extended 80-col card, Ramworks II,
Titan Saturn 128k card, excetera..) set switch 8 to the "ON" position.
Bank Switch Language Card Location:
Dip Switches 1-3 encode the location of your Bank switch language
card. Use the following table to find the appropriate setting for your
machine:
Dip Switch Bank Switch Card Location
1 2 3 Slot #
--- --- --- ------
off off off 0
off off on 1
off on off 2
off on on 3
on off off 4
on off on 5
on on off 6
on on on 7
If you have two bank switch cards in your system, one must reside in
slot 0. The other must be in the slot selected by DIP switches 1-3
above.
Special Note: Because the first three switches are used to encode the
location of the Bank Switch Language Card, you can no longer control the
speed of all the slots. Specifically you can not control slots 1,3, or
6. These slots woll now always run Fast except for slot 6 which will
always run Slow.
Special Note: The slot that the SpeeDemon card resides in should be
set to the "Off" position
____________________________
From: Will Baguhn
009- How can I get a 'Cache Hit' indicator for my ZipGSx?
This latest ZipGSx modification is pretty straightforward. When I
decided I wanted a Cache HIT light instead of a Cache MISS light, I went
to Rat Shack and bought a pack of Green LEDs (I like green. Blue or
Orange will work just as well.)
I tried adding an inverter to the circuit but it just didn't want to
play (obviously a cache HIT is the opposite of a cache MISS, and the LED
on the board lights up for cache MISSes). Through the experimenting, I
found that I could get the LED to light as desired without any "extra"
hardware except the LED itself.
Simple mod: solder in the Anode of the LED to the Anode of the Cache
Miss. Solder the Cathode to the Cathode of the Power LED.
(Even easier way to say it: there are four solder points for the
existing LEDs. We use the two in the middle. The long lead goes to the
yellow side, the short to the red. position as is comfortable. I can
only guess that this would be a nice thing to attach to the TURBO light
on the front of a tower case, should anyone ever mount a IIgs/ZipGSX
inside a tower case... (also, it might be nice to turn SW1-6 OFF and
connect the pins to the TURBO button on front. I don't know how useful
it would be, but it might come in handy one of these days...)
____________________________
From: Clayten Hamacher
010- How can I program the ZipGSx registers?
I asked the same question recently regarding the zip and how to control
it and received a bunch of mail and the following list of registers and
info on how to change them... (I can't remember who sent it to me as it
was a binscii'd file and I didn't save the message it unpacked from.)
ZipChip GS Special Registers Ex ZIP Technology, 12 October 1990
Registers must be unlocked before they can be accessed (see $C05A).
Locking them will re-enable the annunciators.
Writing to any I/O location $C058-$C05F (whether registers are locked or
unlocked) will reset delay in progress.
$C058 R No operation
$C058 W Write any value to force power-on/reset bit to COLD (forces
next reset to restore ZIP registers to defaults/switch settings).
$C059 R/W 76543210
*....... Bank Switch Lang Card cache disable=1/enable=0?
.*...... Padl delay (5 ms) disable=0/enable=1 $C070/$C020
..*..... External delay (5 ms) disable=0/enable=1
...*.... Cntr delay (5 ms) disable=0/enable=1 $C02E/$C07E
....*... CPS follow disable=0/enable=1
.....*.. Last Reset warm? READ ONLY
......*. Hardware DMA READ ONLY
.......* non-GS (0)/GS (1) READ ONLY
$C05A R 76543210
****.... Current ZIP Speed, 0=100%, 1=93.75%,..., F=6.25%
....1111
$C05A W Write values as follows:
$5x Unlock ZIP registers (must write 4 times)
$Ax Lock ZIP registers
other Force ZIP to follow system clock (disable card)
$C05B R 76543210
*....... 1msclk - clock with 1 ms period
.*...... cshupd - Tag data at $C05F updated
(read $C05F to reset)
..*..... Bank Switch Language Card cache (0), don't (1)
...*.... Board disable - 0=enabled, 1=disabled
....*... delay in effect (0=ZIP, 1=Slow)
.....*.. rombank (0/1) - not in development version
......** Cache RAM size (00=8k, 01=16k, 10=32k, 11=64k)
$C05B W Write any value to force ZIP to current speed
(i.e. enable card)
$C05C R/W 76543210
*******. Slot 7-1 delay enable (all slots 52-54 ms)
.......* Speaker delay enable (5 ms)
$C05D R Current 65816 bank
$C05D W 76543210
****.... Set ZIP speed, 0=100%, 1=93.75%, ..., F=6.25%
....**** Don't care
$C05E R Read last Tag data written and force the next write
to create a trash tag value.
$C05E W No operation
$C05F R Read last Tag data written and reset cshupd.
Note: apparently any write to a ZIP register
(unlocked) will clear cshupd, but cshupd
says that this location must be read.
$C05F W No operation
----------------------------
From: David.Empson@actrix.gen.nz (David Empson)
The ProDOS-8 QUIT call should read ...
2000: A9 50 LDA #$50
2002: 8D 5A C0 STA $C05A ; write $50 to $C05A four times to
2005: 8D 5A C0 STA $C05A ; enable access to the ZIP registers
2008: 8D 5A C0 STA $C05A
200B: 8D 5A C0 STA $C05A
200E: 8E 5A C0 STZ $C05A ; write $00 to $C05A to disable ZIP
2011: 0A ASL
2012: 8D 5A C0 STA $C05A ; write $A0 to stop accessing ZIP
2015: 20 00 BF JSR $BF00 ; Do a ProDOS QUIT call
2018: 65 $65
2019: 1D 20 $201D
201B: 00 00 BRK $00
201D: 04 00 00 00 00 00 00
Just type in the hex codes on the left, and use the following commands
to save it:
CREATE SLOW,TSYS
BSAVE SLOW,TSYS,A$2000,L$24
To write FAST, simply change one byte:
200F:5B
(this changes the STZ $C05A to STZ $C05B)
CREATE FAST,TSYS
BSAVE FAST,TSYS,A$2000,L$24
____________________________
From: William Baguhn
Reference: FAQs resource file R005SPLITC
011- Is there some ZipGSx mod that will improve performance
without going to a faster crystal, etc.?
There is; you can do the ZipGSx Split Cache Mod. As your manual
explains, Zip GSX speed comes from having a faster processor which can
access code and data from its high-speed cache RAM. The standard 'GSX
has a unified cache, which means data and code have the possibility of
overlapping. If the cache controller sees a need to bring in a lot of
code, it will go to main memory and bring in up to 64k of code (or 16k
in a 16k cache system) and, possibly, overwrite useful data.
The reverse is also true. If the controller feels that a lot of
data needs to be brought in, it will cache the data, and, possibly,
overwrite useful code, causing another slowdown when the code needs to
be fetched again.
With a split cache, the code and data segments no longer overlap.
Caching code cannot overwrite data, caching data cannot overwrite code.
The drawback is that only 32k of data and 32k of code can be cached at
once (in a 64k system), but usually this provides for more speed than
being able to cache a 64k mix of both.
To do the mod, you'll need a ZipGSX version 1.02 with either 16k or
64k cache on it. If you're not sure exactly what board you have, it's
pretty straightforward to figure things out: open the computer and look
at the Zip. The board revision is silkscreened on just beneath the
processor.
The cache size can be determined from the DIP switch settings.
However, a simpler guideline is look at the TAG/DATA sockets and count
the number of chips. If there are only 2 chips, you have either an 8k or
a 32k cache. If there are 4, then you should have 16k or 64k.
To modify your Zip for the Split Cache, you'll need a good hobby
knife that can cut the traces without damaging the board underneath too
badly, as well as two or three small lengths of wire. You will also need
a good pencil-style soldering iron, desoldering pump or braid, and high
quality rosin core (NOT acid core) solder. I use Radio Shack's .032
60/40 rosin core solder. Kester makes excellent quality solder which is
sold at many electronics supply shops.
There is a potential of damaging expensive and delicate hardware.
For example, when cutting a circuit trace be careful not to cut deeply,
lest you cut a trace in the next layer of the circuit board. If you're
not experienced with cutting traces or soldering on circuit boards, find
an old board and take some time to practice.
The actual mod is very simple. Steps 1-3 and 5 are for all boards.
Step 4 is for 16k cache boards only. (Note: The picture in FAQs resource
file R005SPLITC may be helpful for doing these mods.)
1. Locate J6 and J7. They are both blocks of 3 pinholes, which may or
may not have been soldered-in, near the bottom of the board next to
connector J1, where the gray cable attaches.
2. Cut the SMALL trace between pins 2 and 3 of both J6 and J7. This
trace is on the back (solder side) of the board.
3. Solder in a piece of wire between pins 1 and 3, of both J6 and J7. A
wire that has been bent into a U shape before soldering seems to work
best, both for ease of installation and aesthetic value.
4. 16k systems ONLY: (See the "16k" insert on the picture in FAQs
resource file R005SPLITC.) Cut the trace between pins 1 and 2 of J8 on
the top side of the board. (J8 is below the Cache SRAM sockets) Then,
solder a piece of wire between pins 2 and 3 of J8.
5. Set the DIP switches appropriately. The DIP switches needing to be
set are SW1-7 and SW1-8, they control the cache size. SW1-7 should be
OFF for 64k, ON for 16k. SW1-8 should be ON.
Reversing these changes is fairly easy. If you decide that the
performance change was detrimental, simply desolder the wires that you
installed, and solder in wires to replace the traces that were cut.
I found that the split cache sped up my system notably, especially
under the Finder and other desktop applications. Improvement was much
less noticeable under text applications. (I haven't checked affect on
compiling speed, yet.)
Personally, I think this is an excellent modification, well worth
the time and effort. Splitting the cache probably didn't change the
Dhrystone rating; but, it definitely made my system feel perkier!
____________________________
From: Richard Der
012- I have a 7MHz ZipGS. How fast can the board be pushed without
getting new SRAMs or a new CPU? What parts do I need?
You may be able to get it to run at up to 10MHz by just replacing the
oscillator with a faster one for less than two dollars!
I have a Zip GS that came as a 7/32 and was used at 7MHz for a long
time. The board came with a socketed oscillator, so one day I swapped
out the 28MHz oscillator for a 36MHz one. The computer booted up at
9MHz. When the 36MHz osc was replaced with a 40MHz osc, the Zip ran at
an amazing 10MHz!
Your mileage may vary, though. The GS that this upgraded Zip resides in
has a high output power supply. Still, considering these oscillators
cost $1.39 each, it is worth trying an oscillator swap alone first. If a
faster oscillator alone won't do the trick, then a faster CPU and/or
faster cache chips may be necessary.
Here's what you need to upgrade to 10MHz:
Oscillators