Re: 6502, 65816 = RISC ?

[nathan@visi.com (Nathan Mates)]

In article <nugundamDw9wxq.GEy@netcom.com>,
Joseph Lee <nugundam@netcom.com> wrote:
>Nathan Mates (nathan@visi.com) wrote:
>:    For the third time in as many days, it's THE WAY THE PROCESSOR
>: ACCESSES THE BUS. Not pipelining. Electrically, the 6502 takes 1 (one)
>: clock cycle to read a byte off the bus. The 8086 takes 4 (four). Thus
>: for _ANY_ memory access, the 6502 is 4 times faster than an 8086 at
>: the same clock speed to read that byte. 

>Can you explain what exactly each chip is doing during those cycles when
>it is pulling something off the bus?  Might as well as explain what the
>68000 does at the same time too, because it requires 4 cycles per word (or
>used to).

   Diddling around doing nothing? Multiprocessing and pipelining sure
weren't standard features at the time. If you know that it'll take 4
clock cycles for a byte to show up and you can't do anything else, you
can just program the microprocessor to kill cycles until the data's
ready.

>I always though it was because the 65xxx series did some preprocessing so
>that it could pull stuff off the bus in 1 cycle and that could be called
>pseudo-pipelining in terms of executing an instruction and do processing to
>prepare for the next one.  Of course, it doesn't quite explain why 1 byte/no
>memory access instructions take 2 cycles to execute.

   The only pipelining that Lichty & Eyes (p. 40, by the way) report
the 65xx capable of doing is "performing two different but overlapping
phases of _a_ task within a single cycle" (emphasis mine) and gives
the following example for say 'ADC #val'

1: Fetch instruction byte
2: Interpret instruction to be "ADC #"
3: Fetch value
4: Do the math
5: Store result back in accum

   Lichty & Eyes notes that steps 2&3, 4&5 are combined into one
cycle each. This is a speedup of 2 cycles from a non "pipelined"
design. (Once again, this is still _1_ instruction at a time, not
multiple stages of various instructions at once, as pipelining has
come to mean on modern processors)

   Finally, lower on the page is what I had to repeat a few times this
past week, is their acknowledgment that the 68000 requires _4_ clock
periods (i.e. Cycles) to read or write data to and from memory, while
the 65xx requires 1. Maybe some electrical engineer or 68K/Z80/8086
guru can explain why that road was taken-- probably simpler bus and
memory decoding logic. I believe by the time of the 486 that they
went back to 1 clock cycles simply because of the need for speed.

Nathan Mates

--
<*> Nathan Mates http://www.visi.com/~nathan/      <*>
# What are the facts? Again and again and again-- what are the _facts_?
# Shun wishful thinking, avoid opinion, care not what the neighbors
# think-- what are the facts, and to how many decimal places?  -R.A. Heinlein