Re: 6502, 65816 = RISC ?

[dempson@actrix.gen.nz (David Empson)]

Joseph Lee <nugundam@netcom.com> wrote:

> Nathan Mates (nathan@visi.com) wrote:
> :    For the third time in as many days, it's THE WAY THE PROCESSOR
> : ACCESSES THE BUS. Not pipelining. Electrically, the 6502 takes 1 (one)
> : clock cycle to read a byte off the bus. The 8086 takes 4 (four). Thus
> : for _ANY_ memory access, the 6502 is 4 times faster than an 8086 at
> : the same clock speed to read that byte. 
> 
> Can you explain what exactly each chip is doing during those cycles when
> it is pulling something off the bus?  Might as well as explain what the
> 68000 does at the same time too, because it requires 4 cycles per word (or
> used to).

The difference boils down to how the bus timing signals are generated.

In the more advanced processors, there are signals generated by the
processor or external hardware which explicitly indicate when operations
should occur.  The bus access can be delayed by external circuitry, e.g.
if accessing slow memory, by inserting "wait states", which are clock
cycles in which nothing happens on the bus (the signals are held in
their previous condition).

The 6502 uses a simpler scheme, in which all the timing is fixed
relative to an external clock.  Inherent and forced delays in the
processor are used to get the various operations to occur in the right
order.  One way to implement a "wait state" is to stretch the clock
signal being supplied to the processor.  There is also a RDY (ready)
input, which can be used to delay read cycles only (it can also delay
write cycles on a 65C02 and 65816).  If the processor is replaced with
one rated at a higher speed, the delays are shorter.  This may cause the
system to fail if the delays are too short for external hardware to
handle.


The general sequence of events during a bus access cycle (for most
processors) is as follows:

1. The processor outputs the address to be accessed, along with any
conditioning signals required, e.g. read/write, address space selection
(e.g. program/data).

2. Once the address has stabilised, the processor outputs the control
signals required to trigger a memory access.

3. The processor waits long enough for the memory address to be
processed.

4a. For a write operation, the data to be written is output on the bus,
then the appropriate "write now" signal is generated.

4b. For a read operation, the "read now" signal is generated.

5. The processor waits long enough for the memory read or write to take
place.

6a. For a write operation, the "write now" signal is removed and the
data bus is released.

7a. For a read operation, the processor samples the data provided by
memory and removes the "read now" signal.


Here are the specifics on how the Z80 and 6502 implement their bus
cycles.  The 8088/8086 is somewhat like the Z80, but a few details
differ.  The 68000 is quite different, because it uses an asynchronous
bus instead of a clocked bus.  I don't have full details handy for the
68000.


The Zilog Z80
=============

The Z80 has the following interface signals:

Phi (clock input): max 2.5 MHz for the original Z80, 4MHz for the Z80A.
16-bit address bus
8-bit data bus
MREQ (memory request)
IORQ (I/O request)
RD (read enable)
WR (write enable)
WAIT (wait state)
M1 (machine cycle one)
RFSH (memory refresh)

Each memory access requires three or four clock cycles, or more if wait
states are used.  They are referred to as "T-states" in the Z80
documentation, and are called T1, T2, T3, T4 and TW (wait state).  The
Z80 clock is not used directly in bus cycles - it generates control
signals which are derived from the clock.

The sequence of events varies according to the type of access being
performed.

Opcode Fetch
------------

T1: output the memory address and M1, then activate MREQ and RD half way
through the cycle.

T2: the WAIT input is checked half way through the cycle.  If it is
active, then wait states are inserted until WAIT goes inactive.

T3: the opcode is read from the data bus at the start of T3, then MREQ,
RD and M1 are removed.  The Z80 then outputs a refresh address, and
activates RFSH.  MREQ is activated again half way through T3.

T4: MREQ is deactivated half way through the cycle.  The RFSH signal and
refresh address are removed at the start of the following cycle.

During T3 and T4, the Z80 is decoding the opcode.  It is then ready to
fetch the first operand byte (or perform some other memory access) after
T4.

Memory Read
-----------

T1: output the memory address, then activate MREQ and RD half way
through the cycle.

T2: the WAIT input is checked half way through the cycle.  If it is
active, then wait states are inserted until WAIT goes inactive.

T3: the data in the accessed memory location is read from the data bus
half way through T3.  MREQ and RD are then deactivated.

Memory Write
------------

T1: output the memory address, then activate MREQ half way through the
cycle, and output the data to be written.

T2: the WAIT input is checked half way through the cycle.  If it is
active, then wait states are inserted until WAIT goes inactive.  The WR
signal is then activated.

T3: the WR and MREQ signals are deactivated half way through the cycle.
The data is removed from the data bus at the start of the next cycle.

I/O Read
--------

T1: output the I/O address.

T2: activate IORQ and RD at the start of the cycle.  The WAIT input is
checked half way through the cycle.  If it is active, then wait states
are inserted until WAIT goes inactive.

T3: the data in the accessed I/O location is read from the data bus half
way through T3.  IORQ and RD are then deactivated.

I/O Write
---------

T1: output the I/O address.  The data to be written is output half way
through the cycle.

T2: activate IORQ  and WR at the start of the cycle.  The WAIT input is
checked half way through the cycle.  If it is active, then wait states
are inserted until WAIT goes inactive.

T3: IORQ and WR are then deactivated half way through the cycle.  The
data is removed from the data bus at the start of the next cycle.


The 6502, 65C02, and 65816 (more or less)
=========================================

The 6502 has the following interface signals:

Phi0 (clock input): max 1 MHz for the original 6502, 1.5MHz for the
6502A.  There are Phi1 and Phi2 clock outputs, but they are not used in
the Apple II.  They are used internally by the 6502 as bus signal timing
references.  Phi2 is a delayed copy of Phi0 (the delay is unspecified).
Phi1 is an inverted copy of Phi2, with very little delay.

16-bit address bus
8-bit data bus
R/W (read or write, low for write)
RDY (memory ready)

Each memory access requires one clock cycle.  All memory accesses are
timed relative to Phi2.  External hardware must have access to Phi0,
Phi1 or Phi2.  Phi2 goes low at the start of each cycle.

For the rest of this discussion, I am assuming an original 6502 (rated
at 1 MHz) with a 1 MHz clock.

At the start of each cycle, the 6502 outputs the address to be accessed,
together with the R/W signal.  They are delayed by up to 225 ns from the
falling edge of Phi2.  They are removed from the CPU outputs at least 30
ns into the following cycle.

For a read cycle, the data must be set up by external hardware at least
100 ns before the end of the cycle, and held at least 10 ns after the
end of the cycle.

For a write cycle, the CPU outputs the data at most 175 ns after the
rising edge of Phi2, and holds it for at least 30 ns into the following
cycle.

The memory read or write operation is completed by the rising edge of
Phi2 (at the end of the cycle).

If the RDY signal is used, it must be ready 100 ns after the rising edge
of Phi2 (half way through the cycle).  The CPU then generates wait
cycles until RDY is inactive at the half way point in a subsequent
cycle.  Note that the 6502 only supports the RDY signal for read cycles.

The 65816 provides some extra signals (Valid Program Address and Valid
Data Address, for example), but the fundamental mechanism is the same.


General Notes
=============

The Z80 and similar processors require a faster clock to generate all of
the phases of their complicated bus access cycles.  Most processors of
this type require at least two clock cyles per memory access, usually
three or four cycles.

The 6502 uses simple timing delays relative to a master clock to time
its bus accesses.  These allow it to perform a memory access in a single
cycle, and the clock frequency is generally a third or a quarter of a
similarly rated processor from another family.

The main disadvantage of the 6502's method is that adjusting the clock
speed is difficult, because everything in the system uses fixed timing
based on a master clock.  If the frequency is increased, the entire
system has to deal with it.  By comparison, the Z80 method allows the
frequency to be increased as high as the processor can handle.  If the
resulting speed is too fast for the memory and I/O, wait states are
inserted as required to slow down the access.

It is possible to use the RDY signal to introduce wait cycles on the
6502, but this stops the processor for a whole cycle (and it only works
for read cycles on the original 6502).  With a Z80, wait states can be
introduced in multiples of one third of the memory access cycle time,
allowing more precise adjustment of the bus cycle time.

With more advanced processors (even the 8086), the bus accesses are
somewhat independent of the instruction execution, so the introduction
of wait states doesn't necessarily cause a delay in execution of code
(if enough data has been pre-fetched).

--
David Empson
dempson@actrix.gen.nz
Snail Mail: P.O. Box 27-103, Wellington, New Zealand