Re: ZipGS more stable with slower SRAMS?

[rubywand@aol.com (RUBYWAND)]

In article <Pine.SOL.3.91.960717235820.12237B-100000@moose>, Paul Schultz
<pschultz@med.wayne.edu> writes:

>
>Before I go out and buy slower SRAMS for my ZipGS, could someone
>explain why the ZipGS may be more stable at higher speeds with
>"not-so-fast" SRAMS in the DATA cache (around 35-45ns) instead
>of fast SRAMS (15ns)?
>
>

     It is possible for an IC to cause problems when swapped-in for one
which is significantly slower. If its outputs switch much faster, the
board's power rail may not handle the higher Voltage/time change (dV/dt)
very well. This can result in spikes which false-trigger other circuits.

     Some decoding schemes permit very brief Select pulses, address
shifts, etc.. So long as target IC's (like memories, LSI controllers, ...)
are too slow to respond, these very brief transitions go unnoticed. A much
higher speed IC may be able to respond to very brief 'illegal states' and
the result is a crash.

     Some circuits assume that memory will take some minimum time to turn
off outputs. A much faster memory IC might turn off too fast for the
circuit to perform correctly.  

Rubywand