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Re: companion product for GSBarnDoor

Eric Rucker wrote:


         ...whereas the CPU can only access it every 2
cycles in a best-case scenario, IIRC, which helps - current
accelerators aren't really slowed down by the bus, because the
accelerator can keep the CPU fed with data.

Of course, the cache controller is only able to talk to RAM at 2.8
MHz, whereas the CPU is talking to the cache controller at, in this
case, 30 MHz. At 30 MHz, there WILL be a lot of cache misses, even if
the cache controller is good at prefetching - the CPU can badly outrun
the bus. IIRC the 65816's slowest instructions are 7 cycles.

...

                         ...even the fastest instructions on a 65816
take 2 cycles to execute.


All 65xx(x) processors, to a first approximation, access memory on
every processor cycle, either to fetch the instruction bytes or to
load or store data bytes.

A very good first approximation of the number of cycles any instruction
takes to execute is obtained by adding up the number of bytes in the
instruction and adding a cycle for each data memory access required to
complete the execution.

Occasionally, a page crossing or other internal processor activity
will require a cycle when no memory needs to be accessed.  If the
processor is a 6502, it may access memory anyway, sometimes at
an address that has little to do with the desired operation.  The
65C02 and 65816 may avoid these unnecessary accesses.

Single-byte instructions always require one extra internal processing
cycle during which no memory access occurs, but multi-byte instructions
generally access memory on each cycle.

Perhaps you were thinking about the Ph0/Ph1 alternation of the 65xxx
line, in which memory accesses only occur during half of a clock cycle.
If the memory is capable of 2MHz accesses, as DRAM is in the Apple II,
then the processor uses only half the bandwidth and the other half is
available to the video scanner to refresh the display.

I'm not sure how the IIgs fast memory operates, except that accesses
run at 1MHz when they occur to addresses "shadowed" in the "slow"
RAM space of the traditional Apple II.

-michael

NadaNet and AppleCrate II: parallel computing for Apple II computers!
Home page: http://home.comcast.net/~mjmahon

"The wastebasket is our most important design
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