Re: CACHE????

[Michael Mahon <mahon@cup.hp.com>]

RUBYWAND wrote:
> 
> In article <Pine.SOL.3.91.960628084449.25061A-100000@moose>, Paul Schultz
> <pschultz@med.wayne.edu> writes:
> 
> >.... I also recall posts about people piggy backing sram chips
> >on top of the normal cache chips to give 128K. But, this seems a little
> >bizaar and I always discounted this idea. (Apparently from what I
> remember
> >they claimed to physically solder the legs from one chip to the legs of
> >the chip below it!).
> >
> 
>      It may sound kind of bizaar; however,  the piggy-back soldering
> approach for adding RAM works fine. (You do have lift at least one leg on
> the piggy-backed RAM chips and run a separate wire to the circuit board.)
> NMOS and CMOS IC's are not so delicate as is commonly supposed.
> 
> >Anyway, going above 64K is probably not doable without some significant
> >design changes (significant meaning it isn't a mod that we all could do
> >on our own).
> >
> 
>      We would have to disassemble the Zip-GS ROM code and modify it to
> handle additional banks of cache. Probably, a number of users would be
> willing to handle the PROM burning for those interested in the mod.

It isn't ROM code--it's hardware!  This is in a PLA (or two--I don't
have one myself) and the cache addressing must be done on *every*
cycle of the faster clock.  ROM code is out of the question.


> Rubywand

-michael

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This is my personal opinion, and does not in any way represent
the position of my employer, etc...