Re: RamFAST Cache?

[dempson@atlantis.actrix.gen.nz (David Empson)]

In article <31CFC31B.652C@rmci.net>, Michael Warner  <Mikeal@rmci.net> wrote:
> I was just wondering why when upgrading the ZipGS or the 
> TransWarp you couldn't use more than 64k cache.

Because the cache support circuitry on the cards are not designed to
support more cache.


In the case of the ZIP, there is a special option called "split
cache".  This involves some extensive hardware modifications to the
card.  You end up with separate caches for data and program accesses.
I think it requires adding a second bank of RAM chips in parallel with
the current ones, so that you could have up ot 128K of cache RAM (64K
for code, 64K for data).  I hope that they have allowed for
self-modifying code in the design...

I don't know any more about this, so someone else will have to fill in
the details and/or correct any mistakes in the above.
-- 
David Empson
dempson@actrix.gen.nz
Snail mail: P.O. Box 27-103, Wellington, New Zealand