Re: Apple's next move (was Apple II just won't die.)

[rubywand@aol.com (RUBYWAND)]

In article <sheldonDp51K8.2vr@netcom.com>, sheldon@netcom.com (Sheldon
Simms) writes:


>>[RW] .... RISC offers the advantage of hardware and micro-coding
flexibility.

>RISC processors aren't microcoded, that's one reason why they're fast.

    There are several ways to implement RISC. Some designs employ simple
building-block processors which do, in fact, employ user-alterable
microcode. You can also use modules with clocked and unclocked
programmable logic arrays so that instructions are hard-wired.

    Hardware flexibility is very important, too. Being able to configure
and control in-processor buses, registers, stacks, RAM, and arithmetic
logic unit hardware is a major contributor to RISC efficiency.  


>> [RW] ... a well-designed CIS should always out-perform a RISC
predecessor.

>
>I don't want to sound obnoxious, but are you nuts? One of the basic
tenets
>of RISC is that a simpler instruction set simplifies the hardware and
>allows higher clock speeds. There are plenty of top notch chip desginers
>out there. If a well-designed CISC architecture could outperform a RISC
>architecture, they would be making CISC architectures.

    However good a RIS microprocessor may be, it still ends up executing
programmed code to execute user machine code. One can always take an
optimized RISC design, incorporate more/bigger stacks, registers, etc.,
stick it onto a single substrate, include built-in optimized handling of,
say, 65C832 instructions, and end up with a more efficient, faster CIS
version of the uP. This is what CISC designers have been doing for years.
So long as there is a high demand for the uP, costs continue to drop and
even speedier CISC versions are released.

    Vis-a-vis CISC, RISC modules can be relatively simple and do not
require extensive redesign every couple of years. So, for a time, RISC
users have the advantage of building blocks which incorporate more recent
hardware advances. You can expect to find faster RISC versions at the
start of every new uP generation's development cycle.

    As you noted earlier, to get GS-X launched quickly, it makes sense to
go with a RISC "65C832" rather than wait for actual development and
production of a 65C832 uP chip. Once the new II 'takes off', Apple may
decide that moving to a CISC chip will enhance profits.                


    





Rubywand