Delayed Q3 and DEVSEL?!?

[Sbehrens@contech.demon.co.uk (Soenke Behrens)]

Hi,

I'm looking (out of sheer boredom :) at some old schematics again, and
I stumbled over a bit of a puzzler.

On one schematic, done by a friend, he uses delayed Q3 and DEVSEL
signals as input to decoder GALs. Specifically, there is:

One GAL to decode ROM access, it has what you would expect: the address
bus, IOSEL, IOSTB, R/W, and then a delayed (by two inverters) Q3. What
is he doing here? Trying to make sure he doesn't pick up noise on the
address or data lines?

Two GALs decode addresses for the rest of the circuitry, one of the two
has DEVSEL and Q3 (non-delayed, so what is this good for?), the other
one has DEVSEL, Q3, delayed DEVSEL and delayed Q3. The first GAL looks
after IRQ muxing, bank-switching of I/O space and the like, the
second GAL looks after the CS lines for the chips on the board as well
as R/W decoding and LS245 (buffer) enable/direction.

I am slightly puzzled, to say the least. I can guess at what the delayed
Q3 and DEVSEL are used for: Making sure the address and data lines are
valid. OTOH, that is what DEVSEL is supposed to do already for you,
so ... what gives? And then, what does he use a non-delayed Q3 for? On
a GAL that does nothing more exciting than put interrupts to the
Apple bus and give 2 bits of data to D7 and D6 if so requested?

Maybe some of the hardware developers/dabblers out there have used this
technique and can shed some light on it. I have to admit I am
non-plussed.

Thanks

Soenke

--
Standard disclaimer: My opinions are my own, not those of my employer