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Re: Transwarp GS upgrades
In article <3gupnt$aei@triode.apana.org.au>,
Andrew Roughan <posty@triode.apana.org.au> wrote:
>
> I'm looking at upgrading my 13.75Mhz (using a WDC Engineering 65816) TWGS to
> use the 14Mhz 65816.
You mean it is _already_ running at 13.75 MHz, or you want to move up
to that speed?
> I bought my TWGS with the 32k cache installed. The SRAMS are 35 nanoseconds:
> Mosel
> MS62256A-35NC
> 9124 U 5S
Similar to the ones I have in my faulty ZIP (45 ns Mosels).
> What is the theoretical limit in Mhz that these SRAMS can support?
It is hard to say. It depends on the techniques used by the
accelerator. I would say that in theory, a 35 ns RAM should be fast
enough for 14 MHz, but faster RAM is required on a ZIP if you want to
go that high.
Here is some theory. Bear with me for a minute while I think out loud.
The 65816 generates an address about quarter of the way through the
cycle (based on the speed rating of the processor). This is the
earliest point at which the RAM access could start. The RAM must be
ready to read or write by the end of the cycle, so you have:
Minimum cycle time = 1/(4 * rated processor speed) + (ram access time)
For a 14 Mhz processor and 35 ns RAM, this is 52.86 ns.
The processor would theoretically be able to run at the reciprocal of
this, i.e. 18.92 MHz.
There are other factors that limit this further. For example, the
design of the accelerator may not rely on the address being ready so
early, and only start the RAM access at the half way point in the cycle.
There are also constant delays in the circuitry (propogation delays
through ASICs and logic circuitry, for example) that must be factored
in. We therefore have:
Min cycle time = 1/(4 * rated processor speed) + (RAM access) + (delays)
Assuming typical propogation delays of 20 ns and 35 ns RAM, this would
give you a minimum cycle time of 72.86 ns, and a maximum speed of
13.72 MHz.
If the accelerator started the RAM access at the half-way point, the
minimum cycle time would be 90.71 ns, and the maximum speed would be
11.03 MHz.
There may be other factors, such as having to decode tag RAM before
performing a data RAM access (I think the ZIP reads both RAMs
simultaneously, and cancels the access if the tag information says the
desired byte isn't in the cache).
Without knowing more about the design of the accelerators, I can't
give you an exact formula. I would say that a "safe" formula would be:
Min cycle time = 1/(2 * rated processor speed) + RAM access + 30 ns
Maximum speed = 1 / min cycle time
Turning the formula around, we have:
maximum RAM access = 1/desired speed - 1/(2 * processor speed) - 30 ns
By plugging a few numbers in, this seems too pessimistic. For now,
I'll go with the following, which seems closer to some actual numbers
I've seen.
maximum RAM access = 1/desired speed - 1/(4 * processor speed) - 25 ns
(The formula may be slightly different for the TransWarp and ZIP.)
That would give the following RAM ratings for various clock and
processor speeds.
Clock Processor max RAM speed
7 MHz 7 MHz 82 ns
8 MHz 8 MHz 68 ns
9 MHz 10 MHz 61 ns
10 MHz 10 MHz 50 ns
11 MHz 14 MHz 48 ns
12 MHz 14 MHz 40 ns
13 MHz 14 MHz 34 ns
14 MHz 14 MHz 28 ns
I don't think that is quite right yet - I think you need faster RAM at
higher speeds and slower RAM at lower speeds, so some more fiddling
may be necessary.
If someone can give more definite numbers and details of the internal
operation of the accelerators, I can probably come up with a closer formula.
(Note that the RAMs are often hand picked to use ones that run slightly
faster than their rated speed.)
> For the benefit of Australian and New Zealander netters:
> Standard size TTL oscillators in a metal package are available closer to
> home from
> Clarke & Severn Electronics
Thanks for that information, Andrew. I can get oscillators within NZ,
but they are rather more expensive. I haven't investigated custom
frequencies yet.
--
David Empson
dempson@actrix.gen.nz
Snail mail: P.O. Box 27-103, Wellington, New Zealand