vladitx wrote:
On Dec 23, 4:58 am, "Michael J. Mahon" <mjma...@aol.com> wrote:I'm guessing that the primary difference is that on the IIgs, the speaker is driven by an audio amplifier from the actual speaker toggle logic level, while on all other Apple II's, the speaker is driven by a Darlington driver with a peculiar AC-coupled, DC-clamped input.I never investigated this, by there is very audible asymmetry in each toggle direction. Some day ... yep, definitely.The PWM approach assumes that the Apple II clock is constant frequency, but that is not strictly true, since there is a stretched cycle every horizontal line, or 62 cycles.65, I know it's a typo. :-)
;-)
This introduces a 15kHz sub-cycle timing variation, causing an audible beat which is most apparent under conditions of very low modulation (near silence).Surely you have tried PWM at 15.7 kHz (65 cycles), where no modulation occurs, just slightly inaccurate PWM. Is the carrier that noticeable?
When I was younger, it would have driven me from the room! Today, I probably wouldn't notice it. ;-) More seriously, I think that many users would find it quite audible, making it necessary to low-pass the audio, which would greatly reduce the fraction of people who could practically use it. My first DAC ran at 11.05kHz, and even that frequency was barely audible to me--but it drove the rest of my family crazy! It had the advantage of allowing 6-bit conversion (64 pulse widths), but the necessity of low-pass filtering the output seemed too great a sacrifice in usability. I've never built a software DAC running at 15.7kHz, partly because using it would require resampling all the sound files out there, most of which are at 11.05kHz. It would be pretty easy to try, and the extra 19 cycles would certainly be useful. ;-) One downside is that the maximum variation in pulse width would still have to be 32 cycles, since 64 is unattainable in a 65-cycle loop, and any other choice results in unequal steps. The effect would be a reduction in maximum volume by 46/65. BTW, there would not be significant PWM inaccuracy, since the stretched cycle would always occur at the same point in the loop, causing only a slight nonlinearity in transfer function, but no beat frequency. (If the nonlinearity really mattered, it would be possible to "vapor lock" to horizontal blanking so that the stretched cycle always occurred in a non-pulse-producing part of the loop.) -michael NadaNet and AppleCrate II: parallel computing for Apple II computers! Home page: http://home.comcast.net/~mjmahon "The wastebasket is our most important design tool--and it's seriously underused."