Re: How does the Zip GS chip work?

[dempson@actrix.gen.nz (David Empson)]

In article <1994Apr18.031426.10146@labtam.labtam.oz.au>,
Philip Stephens <philip@labtam.labtam.oz.au> wrote:
>   I'm curious to know how the Zip chip for the Apple //GS works.

It is called the "ZIP GS".  It is more than a chip - it is a whole
card.  The card includes the following:

- High-speed 65816 microprocessor, with appropriate crystal or crystal
oscillator.

- ZIP GS ASIC (Application-Specific Integrated Circuit) which controls
the operation of the card (it is the big square chip).

- Cache RAM (two or four can be installed, either 8k or 32k chips; one
chip in each pair is "tag" RAM, the other is "data" RAM).

- Miscellaneous logic circuitry.

The ZIP GS plugs into a slot and into the microprocessor socket on the
motherboard.


Note that the "Zip Chip" for the Apple II is basically the same design
as the ZIP GS, with a simpler version of the ASIC, 8k of cache RAM and
a 65C02 processor.  The whole lot is bound into a tall "chip" which
plugs directly into the microprocessor socket.

> Does it access RAM and ROM at 8 Mhz, or does it simply cache memory
> in order to obtain an average speed up?

The latter.

Memory access speeds on the motherboard are controlled by external
circuitry (mainly the Fast Processor Interface chip) so that memory
accesses take place at 2.8 MHz (with occasional cycles stolen for
memory refresh if you are accessing fast RAM during a refresh cycle) or
1.023 MHz (when the IIgs is running in slow mode, accessing any
location in bank $E0 or $E1, shadowed I/O location in other banks, or
writing to shadowed video buffers in banks 0 or 1).

On read accesses to RAM or ROM, the ZIP GS checks if the location is
already in the cache; if so, the read takes place directly from the
cache at the full speed of the ZIP.

If the location is not in the cache, the ZIP resynchronises with the
motherboard clock and does a standard motherboard read at 2.8 or 1
MHz.  The data is also placed in the cache.

For RAM writes, the ZIP GS slows down to the standard IIgs speed and
writes to main memory, as well as to the cache.

For I/O reads and writes, I think the ZIP GS always slows down, and
doesn't use the cache.  (By I/O, I mean the $C000 space, not video
buffers.)

The ZIP GS can also handle DMA cycles from slot-based cards.  It
monitors the DMA operation and updates its cache with data read into
memory.

> Also, where does it get the 8 Mhz clock signal from?

A crystal or crystal oscillator on the ZIP GS.  Provided you have a
fast enough processor and cache RAM, you can increase the speed of the
ZIP by using a faster oscillator.  The oscillator runs at four times
the rated processor speed.
-- 
David Empson
dempson@actrix.gen.nz
Snail mail: P.O. Box 27-103, Wellington, New Zealand