Re: Carte Blanche and Apples other than 2e

["Charlie" <charlieDOTd@verEYEzon.net>]

"Alex Freed" <alex_news@mirrow.com> wrote in message 
news:ha9o4o$2lvd$1@adenine.netfront.net...
>
> It came to my attention that the image selection from a keyboard 
> doesn't always work right on a 2GS. I also know that it doesn't 
> work on a 2+. This is not exactly a "bug" - rather the 
> implementation is model specific.
>
> To get the keyboard input CB monitors the Apple bus as it appears 
> on the slot connector. If it detects a read from $C000 and the 
> high bit of the data is set it is taken as a keyboard pressed 
> event. Now it gets a bit technical. The signals available on the 
> bus are Q3 and PH0 among others. In most cases the data is valid 
> on a falling edge of the Q3 signal during PH0 high phase of the 
> system clock. This is fine for latching the keyboard access on a 
> 2+. Unfortunately the 2e uses a different design and the keyboad 
> data becomes valid later than that. It also stays valid longer and 
> can be latched on a falling edge of the ph0 itself. Since the vast 
> majority of the A2s are of the 2e variety I chose to use the 2e 
> timing in the default design.
> If the 2+ timing is preferred it is a single Verilog line change. 
> Unfortunately a fix that would work for *both* is not quite as 
> simple. Not terribly hard either - just make a state machine 
> running off the 50 MHz system clock to latch the data somewhere at 
> the right moment that works for both 2+ and 2e. Chances are it 
> will also work for the GS.
>
> I will probably do it eventually (if nobody does it before I do) 
> but it is  not a first priority.
>
> As for the VGA for GS the current design will support the standard 
> video modes but not GS specific ones and not even the 
> double-hires. Can be done but not the top priority either.
>
> -Alex.

Alex,

Can you put the Xilinx project files some place for download?  I ask 
because the main reason I bought a Carte Blanche card was to try my 
hand at programming the FPGA.  I have zero knowledge of how to do 
that but I've got Xilinx ISE, watched their tutorial video and 
ordered the $12 Diligent parallel port to jtag cable (which seems to 
be coming by mule train).  Still I'd hate to start from scratch.  If 
I could see your code I'd have something to learn from.  I have both 
a //e and a IIgs but the IIgs is the machine I'd prefer to use. Who 
knows maybe I could get the GS graphics working (yeah right :-)

Charlie