mdj wrote:
I did notice this issue though during initial testing last weekend and figured it could be worked around by placing an open-collector inverter against whatever output is driving the ready state LED: simply have the inverters open collector output hold reset low until the FPGA signals it's ready on that line, and when the inverter changes state /RESET will again be pulled high by the Apple II.
Maybe even better - there is an internal signal telling that not only is the configuration finished but the clock DLL is also locked. Can be routed to some FPGA pin and used to drive that inverter. Pins are tri-state before the configuration is done.
Having said that IMHO having to do a CTRL-reset just once after a power-up is not such a big deal.
Will let you know how this goes when I get the time. I'll try out the soft Z-80 on my dev edition card. Any idea when the sources for the designs will be available for download ?
The raw project is available. Send me an e-mail and I'll give you a pointer. NOT to the address I post from here - I don't monitor it due to too much spam.
-Alex.