Re: DMA at 2.8 MHz?

[avogan@desire.wright.edu]

In article <1993May14.120834.14292@actrix.gen.nz>, dempson@swell.actrix.gen.nz (David Empson) writes:
> In article <m0ntXWq-00009QC@crash.cts.com> ncp@gnh-cathouse.cts.com (Neal Pitts) writes:
>> Wait, let me understand this - DMA should be done at 1 MHz because of backward
>> compatability with the IIe or because it's safer to let DMA happen at 1 MHz? 
>> If it's for backward compatability, the Rev. D RamFAST only works on the GS
>> anyway...
> 
> No, DMA should be done at 1 MHz because the slot bus runs at 1 MHz.
> The clock frequency is fixed at 1 MHz, and all the bus signals required
> for DMA are timed relative to that.  If the IIgs is running in fast
> mode, the slot address and data bus are invalid.
> 
> The information in the hardware reference manual vaguely implies that
> DMA works to fast areas of RAM while the IIgs is running at 2.8 MHz.
> What it actually means is that you can do a 1 MHz DMA cycle to fast
> RAM while the IIgs is running in fast mode, but you may cause the
> processor to restart an instruction.
> 
> (To DMA into slow memory, the IIgs must already be running at 1 MHz).
> -- 
> David Empson                                                               
> dempson@swell.actrix.gen.nz    <--- Note my new E-Mail address!            
> Snail mail: P.O. Box 27-103, Wellington, New Zealand 


  Actually you will find that you cannot do DMA above 1Mhz, period.  If it
were possible I would have done it on the RamFAST.  When you pull the DMA
signal the FPI (Fast Processor Interface) chip will sync the entire system
to the 1Mhz signal and then pull the Processor's bus enable signal.  This
allows the address bus and data bus to be driven from the slot area.  Unfort-
unately there are other problems with doing DMA.  The Rom 01 machine has
a bug in the FPI chip such that once in a great while if you pull the DMA
signal while the processor is in high speed mode (2.8Mhz) it will cause a
short RAS signal to the motherboard's drams which has about a 50/50 chance
or corrupting some memory byte out there somewhere.  When I was first
developing the DMA circuit for the RF we thought we could run the processor
in fast mode and just pull the DMA line, wrongo.  It would work for hours
and transfer moocho megabytes of data before the system would crash.  I hooked
up my logic analyzer and saw a short RAS signal on the dras and that shot
that idea out the window.  If you disassemble the code for the RF board you
will see that we set the machine to 1Mhz before doing DMA and then we set it
back when we're done.  This works.

   Now it is possible to transfer data faster than 1 meg/sec.  You have to 
get access to the processor environment.  You can either replace the processor
with a circuit (like the Zip does) or if you have a Zip in place you can
get access to the processor environment via the expansion header on the card.
Note that the TWGS is not capable of giving up the processor environment. That
little header on the TWGS is not an expansion header like they claim.  It is
actually used to attach a test circuit.  If you use the expansion of the Zip
you need to pull the RDY signal to the CPU and then bus enable.  This allows
you to push your address and data onto the bus and transfer data at 2.8
meg/sec.   Actually 2.6 meg/sec with the refresh.  No big sweat.  

      Drew