Re: DMA at 2.8 MHz?

[dat33228@uxa.cso.uiuc.edu (Derek A. Taubert)]

glynnet@zero.cypher.com (Glynne Tolar) writes:

>Here is a thought.  If indeed some devices cad DMA at 2.8 MHz could we modify
>our motherboards to do DMA at 2.8?  I keep thinking of the 1MHz line needing
>to be replaced with a 2.8.  I'm going to have to sit down with the hardware
>reference and see why DMA works and if there is a source for 2.8.  Interesting
>project!

Without modifications, it _might_ be possible based on a few things.  This will
give you some direction in your hardware reference hunting:

1) Find out what the following lines are doing during 2.8 MHz operation:

   Part 2 -> ABDIR.L, ABENB.L, DBDIR.L, DBENB.L 
   Part 7 -> MDIN/OUT, EN425.L

2) Figure out what relation the 2.8MHz clock has to the 7M signal.

But the hardware reference won't help you with this.  I posted this a while ago
with no luck finding an answer:

] Can anybody provide me with an explanation (or a timing diagram) of what
] happens on the GS's 1MHz expansion connectors when the processor is screaming
] along at 2.8MHz?  Phase 0 to the slots comes from the slotmaker (BPH0), and is
] always as 1MHz.  Technote reference, maybe?

Answer these questions, and I'll personally provide you with a spec. for doing
2.8MHz I/O and DMA.  If you don't have any luck, I'll probably have the answers
in about a week when I get my GS into the lab (gotta love 200MHz logic
analyzers).

The other thing to consider, of course, is what kind of havoc DMA at 2.8 MHz
is going to reek on the DRAM refresh scheme (or vice-versa)...

-- 
Derek Taubert                   |  Ask me about TCP/IP for the Apple IIgs!
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