Re: FPI

[David.Empson@bbs.actrix.gen.nz]

In article <w5gZXB4w165w@lablues.UUCP> larry@lablues.UUCP (Lawrance A. Schneider) writes:
> There was a post and many following posts under the heading:
> "ROM 1 vs ROM 3."  Amoungst the "following" was one about RAM
> refresh.  I, using my infinite wisdom, claimed that RAM was
> refreshed on the GS the same way as on the II+ I play with when
> doing electronics.  I was corrected!!!  
> 
> Dave said something similiar.  I then posted the following:

Which 'Dave'?  There are several of us on here.  I seem to recall
posting on this topic earlier, but my name is 'David', not 'Dave'.

> |Thanks Dave and Derek.  Right there on page 14 & 24 of the hardware
> |ref. is exactly what you have outlined.  I guess all the world knows
> |except me!  I guess that is what I get for doing all of my electronics
> |on a II+ and all my programing on a gs.  Where is there more info on
> |this beastie?  How does it work?  Is there a counter somewhere within?
> |How is timing maintained?     Thanks    Larry
> 
> The beastie in question was the "FPI."  So far, there has been no
> follow-up.  Can anyone answer the questions I have about same?

Well, refreshing the fast RAM on the IIgs is one of the lesser
functions of the FPI.  [By the way: in a ROM 03, this chip is labelled
"CYA", and in both versions, the register which controls the speed is
called CYAREG.  I have no idea what "CYA" stands for - FPI is "Fast
Processor Interface".]

If you've read the IIgs Hardware Reference, you've read all the
documentation that there is on the FPI (at least, all that I'm aware of).

The refresh mechanism is pretty simple.  All it needs is a 7 (?) bit
counter.  Every few microseconds, the FPI performs a RAS-only access
to all RAM chips, addressing the row currently selected by the counter.

If the micro is trying to address the fast RAM at the same time, the
FPI causes it to wait.  The micro can access ROM and slow RAM without
interference from the memory refresh.

If the processor is accessing fast RAM exclusively, the net effect of
the cycles stolen for refresh is that the IIgs runs at about 2.5 MHz
instead of its maximum 2.8 MHz.

I'm not sure of the details about how many bits are required in the
counter (it may be 10, to allow for 1 megabit RAMs), or what
differences there are between refreshing the motherboard and RAM
expansion slot, or what the period is between refresh cycles (estimate:
3.3 microseconds).
-- 
David Empson

Internet: David.Empson@bbs.actrix.gen.nz    EMPSON_D@kosmos.wcc.govt.nz
Snail mail: P.O. Box 27-103, Wellington, New Zealand