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Update on Carte Blanche status.
- Subject: Update on Carte Blanche status.
- From: Alex Freed <alex_news@mirrow.com>
- Date: Thu, 13 Aug 2009 01:38:10 -0700
- Newsgroups: comp.sys.apple2
- Organization: Netfront http://www.netfront.net
- User-agent: Thunderbird 2.0.0.22 (Windows/20090605)
- Xref: g2news2.google.com comp.sys.apple2:12721
There are two main reasons the cards are not in your hands yet apart
from the manufacturing delays: the emulated disk support was much less
than perfect and we have discovered a weird unexpected problem - the
eeprom containing the configuration did not reliably program by using
the stock Xilinx tools. The process worked most of the time with the
bigger 500E chips but not with the 250E FPGAs that were supposed to act
exactly the same according to the Xilinx's documentation.
We had to resolve the second issue one way or the other before shipping
the boards and ideally I wanted to improve the default configuration
because there was no easy way to update "it in the field" without extra
hardware. The cheap parallel port JTAG adapter is only $12 from Digilent
but using it is not quite trivial.
So I spent the last month designing an easy way to update the
configuration in the flash eeprom without any extra hardware. I'm happy
to report a success. I had to completely dismantle the hard-wired SPI
controller used in the old version and replace that with a very simple
SPI module controlled by the soft Z80 inside the FPGA. There are several
consequences of this action:
1. MMC/SD reading is now very reliable even with an SD card that was
very flaky with the old design. So the NIBBLE mode is more reliable.
2. More importantly we can now re-program the flash with no extra
hardware from a file on the SD card directly. Takes some 10 seconds and
didn't fail even once yet out of 5 or 6 times tested.
3. On the negative side there is no direct SPI control by the 6502 any
more and I did not have a chance to redesign the ProDOS support using
the new SPI controller.
I feel that (2) is the most important part and since it is now possible
for the user to update the configuration when new stuff is released we
should be able to start shipping as soon as we load and test the boards
with the new configuration.
At the same time the re-configuring is a little dangerous just like
re-flashing a motherboard BIOS. If something goes wrong during the
procedure - a power failure or some other malfunction - it can "brick"
the board and the only way to unbrick will be by using the $12 JTAG
tool. Or a $300 USB JTAG from Xilinx :)
-Alex.