To: Michael J. Mahon Michael J. Mahon wrote:
WRT caching, the benefits of caching can be a factor larger than just single-instruction access to RAM. Cached memory is accessed at high speed in accelerated machines. And being able to execute from RAM and directly address it is a huge speed advantage compared to reading it sequentially or indirectly by storing into a register.
Hi Michael, I came across this support doc on Apple's web site - http://support.apple.com/kb/TA34045?viewlocale=en_US
Excerpt"The gate array is the chip that enables the fast cache RAM method speed-up of the Apple IIc Plus computer. This chip is specific to the 65C02 and the Apple IIc Plus memory map. On one side of the gate array sits the 65C02 (4MHz) and two SRAMs for data cache. On the other side of the gate array is the rest of the Apple IIc Plus (video, I/O, memory, disk drive, ROM, etc.). *The gate array knows which parts of Apple memory may be cached and which may not be (e.g. I/O), and keeps track of which bank of switched memory areas are switched in.*
The cache RAM is transparent and not directly addressable. Data that fills the cache RAM can come from most areas of memory; main RAM, *aux RAM*, ROM, Language card RAM."
----This got me thinking about the what affect, extending the AUX Ram space with additional banks, might have if the gate array is monitoring and caching the original AUX RAM area?
If one flipped pages with out the GA knowing about it, could that not lead to cache/RAM corruption?
I did find a later ZipChip manual that stated up to 2MB of AUX ram would be cached on the //e.
Now I wonder if that feature was kept in the version that was used in the //c+?
It would be nice if we could positive confirmation that any of the Zram boards actually work in a //c+
I have a Z-Ram Ultra II but it needs some pin repair first. Glenn