Re: Carte Blanche

[alex.freed.007@gmail.com]

On Apr 17, 2:50 pm, "a2retro" <a2re...@a2central.com.remove-13j-this>
wrote:
> Hi Alex, the Applelogic web site specified the Carte Blanche with
>
>  >> A Xilinx XC3S500E, 500,000 logic gate FPGA for processing,
> combinational logic and interface
>
>  >> On board 512k x8 8ns high speed SRAM for cache and ROM images
>
> I take it you guys decided to tone that down a bit?

It's a matter of price performance. Once we realized that anything
we can think of fits nicely into a smaller and cheaper FPGA we
decided to try and keep the price reasonable.

For example the 6809 Mill configuration uses 1% of the gates
with a real 6809E. My VGA interface uses about 4% of logic.
If you know of a reasonable application that will NOT fit into
250,000 gates let me know. The 500,000 gate chips are pin
compatible. Maybe Steve will make a special version for you.

>
>  >> 8Mbit onboard flash for bitstreams and ROM images
>
> Is the flash still on there?

Sure. That is needed to store the configuration. FPGAs are
RAM based.

-Alex.