Re: IIgs peculiarities

[vladitx <vladitx@nucleusys.com>]

On Feb 22, 10:40 pm, demp...@actrix.gen.nz (David Empson) wrote:

> The point is that it was a decision by the user whether or not to enable
> Alternate Display Mode, so some software could have made the (bad)
> assumption that it was safe to use this area, because the author wasn't
> aware of that feature, or didn't expect it to be enabled.

Ok, reasonable enough. I'm happy enough that "Alternate Mode" on 03 is
done in hardware.

> Same for a ROM 1 or ROM 3. If you enter the CDA menu while the monitor
> is waiting for input, the speed register is temporarily changed, but the
> monitor's KEYIN routine restores it to the prior setting as soon as you
> press a key. (Or it might be the line input routine - I'm just aware of
> never being able to have the speed setting "stick" when entering the CDA
> menu while the standard line input routine is waiting for input.)

I tried with a short BASIC program drawing a circle. Speed definitely
changed (and probably CDA accessed from BASIC prompt), but
nevertheless - same value in $C036.

I will do the test once again when I get back home in few days.

> > I still wonder what "MSIZE" signal does. It is shorted to ground on a
> > certain memory expansion board, so must be input to FPI.
>
> (Without checking documention which is buried away...) It tells the FPI
> whether the memory rows are 256 KB or 1 MB, and thus how to set up the
> CROW memory mapping, and it may influence refresh cycles.

Correct. I found that bit of info in the IIgs Hardware Reference.

Problem with scanned copies is that one cannot search. :-)

> There is a DMA bank select register in the FPI which allows DMA to any
> bank, but the FPI only outputs the CROW signals during a DMA cycle. It
> doesn't output the DMA register in the first half of the cycle.

I found a paragraph about DMA, too. Still unclear, but as far as I
understood it, Mega II gets in touch with FPI to organize DMA to fast
RAM.
I have to research more.

> The bank number is output on the data bus by the 65816 in the first half
> of a CPU cycle, from which it is latched by the FPI.

Yep, found that as well.

> > Are you sure DMA can have I/O in a bank different than $E0?
>
> 100% certain. See above, and every IIgs-specific DMA card (including
> Apple's own "High Speed" SCSI card) fully supports DMA up to the 4 row
> limit in the memory expansion card (plus all of the built-in RAM).

Is there any document besides Hardware Reference which sheds light to
the DMA?

> > Speaking of which, does anyone have schematics of ROM 03?
> They are in the 2nd edition of the IIgs Hardware Reference.

My scanned copy doesn't have the Addendum.



Thanks for helping clearing the mist, David.