To: Steven Hirsch Steven Hirsch wrote:
a2retro wrote:To: a2retro a2retro wrote:alex.freed.007 wrote:The 128K version is particularly easy to use with a battery back-up asit has an active high second chip select. Most likely just adding a> diode and a coin cell will make it NV.I have seen this implemented on a few other projects. zxmmc+ for example.I plan to use this approach for my //cmxp project.Cypress also has an interesting part CY14B104L-ZS45XC - combo SRAM/Flash with autosave.GlennFor anyone updating their card to a 512K ram - double check the datasheet from your vendor of choice, as I see there doesn't seem to be a standard on pin A17 and A18. They are interchanged across vendors.Hmm. All the static memory I've seen (628512LP-70 and AS6C4008-55) have A17 on pin 30 and A18 on pin 1. Are you saying that the SRAM/Flash differs?
Sorry if I led you astray by posting it under the reference to the SRAM/FLASH part
Some examples Page 2 >http://download.cypress.com.edgesuite.net/design_resources/datasheets/contents/cy62148e_8.pdf 32 PIN SOIC A17 - pin 1 A18 - pin 30 page 3 http://www.issi.com/pdf/61-64C5128AL.pdf 32 pin SOP A17 - pin 1 A18 - pin 30 Page 2 http://www.alliancememory.com/pdf/AS6C4008%20feb%202007%20with%20tsop%2011.pdf 32 PIN SOP/DIP A17 - pin 30 A18 - pin 1 page 3 http://documentation.renesas.com/eng/products/memory/rej03c0077_r1lp0408c.pdf 32 pin SOP A17 - pin 30 A18 - pin 1In my case I was planning to use the cypress cy62148E SRAM SOIC on a DIP adapter. It cannot be a one to one mapping as I assumed.
Glenn