Re: Stellation Mill 6809 card clone / FPGA

[David Wilson <mcs6502@gmail.com>]

On Jan 13, 2:54 pm, MdntTrain <j...@cimmeri.com> wrote:
> Alex, Given that CPUs are available (yes, Steve H), does it make sense
> to implement this in an FPGA?   Seems really easy with just SSI
> components... or maybe some PALs?

I would probably design a Mill replacement using only DIL parts - CPU,
ROM and CPLD (GAL) plus possibly a buffer or two. Should fit into a
card no longer than the edge connector and not require such fine
soldering skills as an FPGA design. If I were getting one
professionally manufactured/assembled then that would change things.

Lucky those Jameco parts are 6809E and not 6809 as the external clock
version is needed by the mill design.