Re: Apple ][ to VGA monitor adapter board - looking for best colordecoding method

["Ferdinan Meyer-hermann" <ferdinan.meyer-hermann@a2central.com.remove-eek-this>]

  To: Alex Freed
Alex Freed wrote:

> Ferdinan Meyer-hermann wrote:
>> manual: I have severe difficulties with the circuit description: I
>> understand my circuit, because I designed it, and it's very difficult to
>> explain to someone who has not designed it... Maybe someone could help me
>> with that by asking questions?
> 
> I can try to help but I need to see the circuit.

Thank you! there it is:
http://ferdimh.homelinux.net/apple2/apple2vga/apple2vga2.pdf

Most of the circuitry should be self-explanatory, the following things are
tricky (and sometimes a bit ugly, I think):
Timing:
- In D1 there is a 4.7K resistor in series with the sync line. It causes a
  little delay to solve a race condition between SYNC and COLOR REFERENCE.
- 28M is generated by delaying 14M through three gates (approx 90° phase 
  shift and XORing it.)
- the RC circuit at B10 generates a short pulse so that the load will only
  last one 28M cycle. I consider this to be very ugly, but I doing it
  correctly would need another chip. 

Sync generation:
- The HSYNC flip-flop is set every time the Horizontal scanner is preset
  (i.e. at the beginning of every line) and reset when F2 rises for the
  first time, which is 5 periods of COLOR REFERENCE (1.4us) later.
- VSYNC is the state of the SYNC line 28us after the falling edge of SYNC.
  This scheme should work in any apple, but it is only tested in a //e.

Bus interface:
- There is a flip-flop that duplicates the HIRES/LORES switch on the
  motherboard, with full address decode. The softswitches are implemented as
  one large switch with many settings. the mode can be set with one access
  to the card's address space.
- D3 at B2 serves a purpose to allow the card to be detected. If the card's  
  ROM space is addressed, the high bit of the data bus will be forced to
  zero. So a controlling program must read the whole ROM space and check if
  the high bit is always reset. The screen shall be in text mode at that
  time, so that the high bit is always set (assuming it is cleared).
  This scheme will not interfere with any card because reading the ROM space
  should always be safe.


- Graphics time from the motherboard is delayed by 1 horizontal period.
  Because it is asserted before SYNC it needs to be latched twice.
  If GRAPHICS TIME was not delayed, the mode switching would happen while
  the last line of graphics is still being output.

- in the video output AC devices are used because of their higher drive    
  capability.

- The resistor matrix cannot be explained. it was determined experimentally
  (and I'm still not confident with it)


Ferdinand
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